IP Library Granted Patent US 7,378,352
Granted Patent B2
US 7,378,352 · App. 11/411,043 · Granted May 27, 2008

Method of fabricating semiconductor device

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Quick Facts
Patent No.
US 7,378,352
App. No.
11/411,043
Granted
May 27, 2008
Kind
B2
Abstract

After low dielectric constant films are formed on a wiring, hardmasks are formed on the low dielectric constant films. A resistmask is formed on the hardmasks. Via holes are formed in the low dielectric constant films using the resistmask. Ashing the resistmask is performed. During this process, a protection film is formed by sticking a sputtered material generated from the resistmask at least onto side surfaces of the via holes. Thereafter, the via holes are extended to the wiring, and a conductive material is buried into the via holes.

Claims (54)

1. A method of fabricating a semiconductor device, comprising:

forming an inorganic low dielectric constant film over a wiring;

forming a hardmask over the inorganic low dielectric constant film;

forming a resistmask over the hardmask;

forming an opening in the inorganic low dielectric constant film using the resistmask;

ashing the resistmask with forming a protection film by sticking a sputtered material generated from the resistmask at least onto a side surface of the opening by using O 2 plasma;

extending the opening to the wiring; and

burying a conductive material in the opening,

wherein ashing the resistmask includes applying a substrate voltage of less than or equal to −300 V to a substrate above which the inorganic low dielectric constant film is formed.

2. The method of fabricating a semiconductor device according to claim 1 wherein, as the opening, a via hole in a dual damascene method is formed.

3. The method of fabricating a semiconductor device according to claim 1 wherein ashing the resistmask includes sputter-etching the resistmask.

4. The method of fabricating a semiconductor device according to claim 1 further comprising, between ashing the resistmask and extending the opening to the wiring, sticking onto the protection film a sputtered material generated from the hardmask by sputter-etching the hardmask during over-ashing the resistmask.

5. The method of fabricating a semiconductor device according to claim 1 wherein, as the hardmask, one selected from the group consisting of a SiN-based film, a SiC-based film, a SiOC-based film, a C-based film, a Ta-based film, and a Ti-based film is used.

6. The method of fabricating a semiconductor device according to claim 1 further comprising, between forming the protection film and extending the opening to the wiring:

forming a second resistmask over the hardmask;

patterning the hardmask using the second resistmask;

ashing the second resistmask with sticking a sputtered material generated from the second resistmask at least onto the side surface of the opening; and

forming a second opening in the inorganic low dielectric constant film using the hardmask.

7. The method of fabricating a semiconductor device according to claim 6 wherein, as the second opening, a wiring trench in a dual damascene method is formed.

8. A method of fabricating a semiconductor device comprising:

forming an inorganic low dielectric constant film over a wiring;

forming a hardmask over the inorganic low dielectric constant film;

forming a resistmask over the hardmask;

forming an opening in the inorganic low dielectric constant film using the resistmask;

ashing the resistmask;

forming a protection film by sticking a sputtered material generated from the hardmask by sputter-etching the hardmask during over-ashing the resistmask at least onto a side surface of the opening by using O 2 plasma;

extending the opening to the wiring; and

burying a conductive material in the opening,

wherein ashing the resistmask includes applying a substrate voltage of less than or equal to −300 V to a substrate above which the inorganic low dielectric constant film is formed.

9. The method of fabricating a semiconductor device according to claim 8 wherein, as the opening, a via hole in a dual damascene method is formed.

10. The method of fabricating a semiconductor device according to claim 8 further comprising, between forming the protection film and extending the opening to the wiring:

forming a second resistmask over the hardmask;

patterning the hardmask using the second resistmask;

ashing the second resistmask with sticking a sputtered material generated from the second resistmask at least onto the side surface of the opening; and

forming a second opening in the inorganic low dielectric constant film using the hardmask.

11. The method of fabricating a semiconductor device according to claim 10 wherein, as the second opening, a wiring trench in a dual damascene method is formed.

12. The method of fabricating a semiconductor device according to claim 10 wherein, in ashing the resistmask, one selected from a group consisting of an oxygen plasma, an ammonia plasma, and a hydrogen plasma is used as an ashing plasma.

13. A method of fabricating a semiconductor device comprising:

forming an inorganic low dielectric constant film over a wiring;

forming a hardmask over the inorganic low dielectric constant film;

forming a first resistmask over the hardmask;

forming a first opening in the inorganic low dielectric constant film using the first resistmask;

ashing the first resistmask;

forming a second resistmask over the hardmask;

patterning the hardmask using the second resistmask;

ashing the second resistmask with forming a protection film by sticking a sputtered material generated from the second resistmask at least onto a side surface of the first opening by using O 2 plasma;

forming a second opening in the inorganic low dielectric constant film using the hardmask;

extending the first opening to the wiring; and

burying a conductive material in the first and second openings,

wherein ashing either or both of the resistmask includes applying a substrate voltage of less than or equal to −300 V to a substrate above which the inorganic low dielectric constant film is formed.

14. The method of fabricating a semiconductor device according to claim 13 wherein, as the first opening, a via hole in a dual damascene method is formed, and as the second opening, a wiring trench in the dual damascene method is formed.

15. The method of fabricating a semiconductor device according to claim 13 wherein ashing the second resistmask includes sputter-etching the second resistmask.

16. The method of fabricating a semiconductor device according to claim 13 further comprising, between ashing the second resistmask and forming the second opening, over-ashing the second resistmask on a condition where a substrate voltage applied to a substrate above which the inorganic low dielectric constant film is formed is set to be weaker than when the second resistmask is ashed.

17. The method of fabricating a semiconductor device according to claim 13 wherein, in ashing the second resistmask, one selected from a group consisting of an oxygen plasma, an ammonia plasma, and a hydrogen plasma is used as an ashing plasma.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2006
From: IBA, YOSHIHISA
To: FUJITSU LIMITED
Reel/Frame 017817/0225 →