IP Library Granted Patent US 7,646,027
Granted Patent B2
US 7,646,027 · App. 11/416,112 · Granted Jan 12, 2010

Group III nitride semiconductor stacked structure

Assignee: Showa Denko K.K.
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Quick Facts
Patent No.
US 7,646,027
App. No.
11/416,112
Granted
Jan 12, 2010
Kind
B2
Abstract

An object of the present invention is to provide a Group III nitride semiconductor stacked structure with a low dislocation density obtained by stacking only a semiconductor layer on a flat substrate by the use of a normal epitaxial growth method without processing the substrate or a deposit layer on the substrate, wherein the dislocation density is 1×10 7 cm −2 or less. The inventive Group III nitride semiconductor stacked structure comprises a substrate having a surface roughness (Ra) of 1 nm or less and a Group III nitride semiconductor layer directly stacked on the substrate, wherein the Group III nitride semiconductor layer comprises a plurality of layers put into contact with each other, the plurality of layers comprise a high-concentration impurity atom layer and a low-concentration impurity atom layer, and the high-concentration impurity atom layer is present on the substrate side.

Claims (13)

1. A stacked structure for a Group III nitride semiconductor device, comprising a flat substrate having a surface roughness (Ra) of 1 nm or less and a Group III nitride semiconductor layer directly stacked on the substrate, the Group III nitride semiconductor layer comprising a plurality of layers put into contact with each other, at least a pair of layers out of the plurality of layers put into contact with each other being a high-concentration impurity atom layer and a low-concentration impurity atom layer, the thickness of the high-concentration impurity atom layer being from 0.5 to 3 μm, the high-concentration impurity atom layer being present on the substrate side, wherein pits are present in the range from 1×10 5 cm −2 to 5×10 8 cm −2 on the surface of the high-concentration impurity atom layer opposite the substrate, and

at least one of the plurality of layers being a layer having a dislocation density of 1×10 7 cm −2 or less.

2. The stacked structure for a Group III nitride semiconductor device according to claim 1 , wherein a high-concentration impurity atom layer and a low-concentration impurity atom layer are present alternately and periodically.

3. The stacked structure for a Group III nitride semiconductor device according to claim 2 , wherein the periodic number is from 1 to 10.

4. The stacked structure for a Group III nitride semiconductor device according to claim 1 , wherein the impurity is one member selected from the group consisting of Si, Ge, Sn, S, Se, Mg and Zn, or a combination of two or more members selected therefrom.

5. The stacked structure for a Group III nitride semiconductor device according to claim 4 , wherein the impurity is Ge.

6. The stacked structure for a Group III nitride semiconductor device according to claim 1 , wherein the impurity concentration of the high-concentration impurity atom layer is from 5×10 17 to 4×10 19 cm 31 3 .

7. The stacked structure for a Group III nitride semiconductor device according to claim 1 wherein the impurity concentration of the low-concentration impurity atom layer is lower than the impurity concentration of the high-concentration impurity atom layer and is 2×10 19 cm −3 or less.

8. The stacked structure for a Group III nitride semiconductor device according to claim 7 , wherein the low-concentration impurity atom layer is not intentionally doped with an impurity.

9. The stacked structure for a Group III nitride semiconductor device according to claim 1 wherein the thickness of the low-concentration impurity atom layer is from 0.1 to 10 μm.

10. The stacked structure for a Group III nitride semiconductor device according to claim 1 , wherein the entire thickness of the high-concentration impurity atom layer and the low-concentration impurity atom layer is from 1 to 1,000 μm.

11. A Group III nitride semiconductor light-emitting device having an n-type layer, a light-emitting layer and a p-type layer in this order, each comprising a Group III nitride semiconductor layer, on the stacked structure for a Group III nitride semiconductor device according to claim 1 , in which a negative electrode and a positive electrode are provided on the n-type layer and the p-type layer, respectively.

12. A lamp comprising the light-emitting device according to claim 11 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2012
From: SHOWA DENKO KABUSHIKI KAISHA
To: TOYODA GOSEI CO., LTD.
Reel/Frame 029489/0249 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2006
From: BANDOH, AKIRA
To: SHOWA DENKO K.K.
Reel/Frame 017860/0476 →
Priority Claims (1)
JP 2005-134926 · May 6, 2005 · national
Continuity (2)
Provisional Application 6067997800 · May 12, 2005
Related Publication 20060261353A1 · Nov 23, 2006