Method for determining wordline critical dimension in a memory array and related structure
View Patent ↗According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.
1. A method for fabricating a memory array, said method comprising steps of:
forming a plurality of trenches in a substrate, said plurality of trenches determining a plurality of wordline regions in said substrate, each of said plurality of wordline regions being situated between two adjacent trenches in said plurality of trenches, said each of said plurality of wordline regions having a wordline region width;
forming a plurality of bitlines in said substrate, said plurality of bitlines being situated in a direction perpendicular to said plurality of trenches;
forming a dielectric region in each of said plurality of trenches;
forming a dielectric stack over said plurality of bitlines, said plurality of wordline regions, and said plurality of trenches;
forming a plurality of wordlines, each of said plurality of wordlines being situated over one of said plurality of wordline regions;
wherein said wordline region width determines an active wordline width of said each of said plurality of wordlines.
2. The method of claim 1 wherein said step of forming said dielectric region in each of said plurality of trenches comprises steps of:
depositing a layer of silicon oxide over said plurality of trenches and said plurality of wordlines regions;
planarizing said layer of silicon oxide to expose a top surface of said each of said plurality of wordline regions.
3. The method of claim 1 further comprising a step of forming a plurality of masking lines on said substrate prior to said step of forming said plurality of trenches in said substrate, wherein each of said plurality of masking lines has a masking line width, wherein said masking line width is substantially equal to said active wordline width.
4. The method of claim 1 wherein said dielectric stack comprises an ONO stack.
5. The method of claim 1 wherein said each of said plurality of trenches has a depth of between 400.0 Angstroms and 600.0 Angstroms.
6. The method of claim 1 further comprising a step of forming a plurality of memory cells, wherein each of said plurality of memory cells is formed at an intersection of a region between adjacent bitlines in said plurality of bitlines and one of said plurality of wordlines, wherein said each of said plurality of memory cells is a flash memory cell.
7. The method of claim 6 wherein said flash memory cell is a two-bit flash memory cell.
8. The method of claim 1 wherein said memory array is a flash memory array.
9. A memory array comprising:
a plurality of trenches situated in a substrate;
a plurality of wordline regions situated in said substrate, each of said plurality of wordline regions being situated between two adjacent trenches in said plurality of trenches, said each of said plurality of wordline regions having a wordline region width;
a plurality of bitlines situated in said substrate, said plurality of bitlines being situated perpendicular to said plurality of wordline regions;
a plurality of wordlines, each of said plurality of wordlines being situated over one of said plurality of wordline regions;
a plurality of dielectric regions, wherein each of said plurality of dielectric regions is situated in one of said plurality of trenches;
a dielectric stack situated over said plurality of bitlines, said plurality of wordline regions, and said plurality of trenches;
wherein said wordline region width determines an active wordline width of each of said plurality of wordlines.
10. The memory array of claim 9 wherein said dielectric stack comprises an ONO stack.
11. The memory array of claim 9 further comprising a plurality of memory cells, wherein each of said plurality of memory cells is situated at an intersection of a region between adjacent bitlines in said plurality of bitlines and one of said plurality of wordlines, wherein said each of said plurality of memory cells is a flash memory cell.
12. The memory array of claim 11 wherein said flash memory cell is a two-bit flash memory cell.
13. The memory array of claim 9 wherein each of said plurality of trenches has a depth of between 400.0 Angstroms and 600.0 Angstroms.
14. The memory array of claim 9 wherein said plurality of dielectric regions comprise silicon oxide.
15. The memory array of claim 9 wherein said each of said plurality of wordlines has an actual wordline width, wherein said actual wordline width is greater than said active wordline width.
16. The memory array of claim 9 wherein said memory array is a flash memory array.