Non-volatile multi-level semiconductor flash memory device and method of driving same
View Patent ↗In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
1. A nonvolatile memory comprising:
a plurality of memory cells,
a plurality of word lines, each of which couples to corresponding ones of said memory cells,
wherein said nonvolatile memory is capable of receiving a plurality of commands which include a read command accompanied with a read address and a discriminating address discriminating bits in the memory cells,
wherein said nonvolatile memory is adapted to perform either a first read operation or a second read operation according to the discriminating address,
wherein, in the first read operation, the nonvolatile memory is adapted to output the data by selecting one of the plurality of word lines once, and
wherein, in the second read operation, the nonvolatile memory is adapted to output the data by selecting one of the plurality of word lines twice.
2. A semiconductor memory according to claim 1 ,
wherein, in the first read operation, a first voltage is supplied to the selected one of the plurality of word lines,
wherein, in the second read operation, a second voltage is supplied to the selected one of the plurality of word lines and then a third voltage is supplied to the selected one of the plurality of word lines, and
wherein the first voltage is between the second voltage and the third voltage.
3. A semiconductor memory according to claim 1 , further comprising:
a plurality of data lines, each of which couples to a corresponding one of said memory cells; and
a plurality of sense amplifiers, each of which couples to a corresponding one of said plurality of data lines,
wherein the nonvolatile memory is adapted to pre-charge the plurality of data lines according to the data held in the sense amplifiers after the second voltage is supplied to the selected one of the plurality of word lines.
4. A semiconductor memory according to claim 2 ,
wherein the second voltage is larger than the third voltage.