Memory architecture and cell design employing two access transistors
View Patent ↗An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs.
1. A memory cell for an integrated circuit, comprising:
a memory element for storing a logic state, the memory element having a first terminal and a second terminal, wherein the second terminal of the memory element is connected to a bit line;
a first access transistor having first and second channel terminals, wherein a first channel terminal of the first transistor is coupled to the first terminal of the memory element, and wherein the second terminal of the first access transistor is connected to a reference potential; and
a second access transistor having first and second channel terminals, wherein a first channel terminal of the second transistor is coupled to the first terminal of the memory element, and wherein the second terminal of the second access transistor is connected to the reference potential,
wherein the first channel terminals of the first and second access transistors comprise a common diffusion region in a substrate, and
wherein the first and second access transistors are independently selectable by respective first and second word lines.
2. The memory cell of claim 1 , wherein the second channel terminals of the access transistors do not share a common diffusion region in the substrate.
3. The memory cell of claim 1 , wherein the memory element comprises a phase change material.
4. The memory cell of claim 1 , wherein the memory element comprises a fuse or antifuse.
5. The memory cell of claim 1 , wherein the memory element comprises a RRAM memory element or a MRAM memory element.
6. The memory cell of claim 1 , wherein the memory element comprises a capacitor.
7. The memory cell of claim 1 , wherein the memory element is formed above the substrate.
8. The memory cell of claim 7 , wherein the memory element is formed above the first and second access transistors.