Performing useful computations while waiting for a line in a system with a software implemented cache
View Patent ↗Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.
1. A method, in a data processing device, for handling software cache misses, comprising:
processing a software cache lookup instruction in a program;
performing a software cache lookup operation;
determining if the software cache lookup operation results in a cache miss;
initiating, by a cache miss handler, a retrieval of data from a backing store in response to results of the software cache lookup operation resulting in a cache miss; and
branching, by the cache miss handler, execution to an independent subroutine that executes while execution of the program waits for retrieval of the data from the backing store, wherein:
the independent subroutine is compiled into a separate subroutine that is stored in a known address location,
the known address location is passed into the cache miss handler as a parameter to thereby cause the cache miss handler to execute the independent subroutine at the known address location after initiating retrieval of data from the backing store,
initiating a retrieval of data from a backing store is performed in a first thread of execution and branching execution to an independent subroutine is performed in a second thread of execution,
useful work is performed during cache miss handling by performing a thread switch operation between the first and second threads, and
the compiler specified independent subroutine comprises a code sequence that does not cause another cache miss due to the independent subroutine being a portion of code that does not reference a portion of code associated with the software cache lookup instruction, does not reference variables that are common between the independent subroutine and the portion of code associated with the software cache lookup instruction, and does not reference aliases of variables used in other portions of code.
2. The method of claim 1 , further comprising:
partitioning registers into a first set of registers for use by the first thread of execution and a second set of registers used by the second thread of execution.
3. The method of claim 1 , further comprising:
storing a current state of registers required by the independent subroutine to another storage location before executing the independent subroutine; and
restoring the current state from the other storage location after completing execution of the independent subroutine.
4. An apparatus for handling software cache misses, comprising:
a processor; and
a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
process a software cache lookup instruction in a program;
perform a software cache lookup operation;
determine if the software cache lookup operation results in a cache miss;
initiate, by a cache miss handler, a retrieval of data from a backing store in response to results of the software cache lookup operation resulting in a cache miss; and
branch, by the cache miss handler, execution to an independent subroutine that executes while execution of the program waits for retrieval of the data from the backing store, wherein:
the independent subroutine is compiled into a separate subroutine that is stored in a known address location,
the known address location is passed into the cache miss handler as a parameter to thereby cause the cache miss handler to execute the independent subroutine at the known address location after initiating retrieval of data from the backing store,
initiating a retrieval of data from a backing store is performed in a first thread of execution and branching execution to an independent subroutine is performed in a second thread of execution,
useful work is performed during cache miss handling by performing a thread switch operation between the first and second threads, and
the compiler specified independent subroutine comprises a code sequence that does not cause another cache miss due to the independent subroutine being a portion of code that does not reference a portion of code associated with the software cache lookup instruction, does not reference variables that are common between the independent subroutine and the portion of code associated with the software cache lookup instruction, and does not reference aliases of variables used in other portions of code.