On-chip supply regulators

1. An integrated circuit, comprising:

an initialization circuit to assert an initialization signal during powering up of the integrated circuit;

a control circuit coupled to the initialization circuit; and

a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted.

2. The integrated circuit of claim 1 , wherein the integrated circuit is implemented on a single chip.

3. The integrated circuit of claim 2 , further comprising:

a digital television demodulator.

4. The integrated circuit of claim 3 , wherein the digital television demodulator comprises a digital circuit and an analog circuit.

5. The integrated circuit of claim 4 , wherein the digital circuit is implemented using complementary metal oxide semiconductor (CMOS) logic.

6. The integrated circuit of claim 4 , wherein the power supply regulator provides one voltage to the digital circuit and one voltage to the analog circuit.

7. The integrated circuit of claim 6 , wherein the voltage to the digital circuit is lower than the voltage to the analog circuit.

8. The integrated circuit of claim 6 , wherein the voltage to the digital circuit is adjustable according to a control signal from the control circuit.

9. The integrated circuit of claim 8 , wherein the control circuit is a digital circuit.

10. The integrated circuit of claim 1 , further comprises a clock generator.

11. The integrated circuit of claim 10 , wherein when the initialization signal is not asserted, the power supply regulator changes the first voltage to the second voltage.

12. The integrated circuit of claim 1 , wherein the power supply regulator comprises:

a load simulator;

a master driver to provide a voltage to the load simulator;

a comparator to generate a control signal based on a difference between a reference voltage and the voltage to the load simulator, wherein the reference voltage is under the control of the control logic;

a slave driver to provide an output voltage;

wherein the control signal from the comparator controls the master driver and the slave driver.

13. The integrated circuit of claim 12 , wherein the load simulator comprises at least one digital gate.

14. The integrated circuit of claim 13 , wherein the reference voltage is generated on the integrated circuit.

15. An integrated circuit, comprising:

means for asserting an initialization signal during powering up of the integrated circuit;

means for generating a control signal;

means for providing a first voltage to generate the control signal when the initialization signal is asserted and providing a second voltage according to the control signal when the initialization signal is not asserted.

16. The integrated circuit of claim 15 , wherein the integrated circuit is implemented on a single chip; and the control signal is programmable to adjust a voltage provided to generate the control signal.

17. The integrated circuit of claim 15 , further comprising:

means for reducing a variation of a voltage to a digital circuit on the integrate circuit and a voltage to an analog circuit on the integration circuit.

18. The integrated circuit of claim 17 , wherein the analog circuit comprises a gain amplifier, Analog to Digital Converter (ADC), reference, biasing and clocking circuitry; and the digital circuit comprises a quadrature amplitude modulation (QAM) demodulator.

19. A process implemented on an integrated circuit, the process comprising:

asserting an initialization signal during powering up of the integrated circuit;

generating a control signal; and

providing a first voltage to a digital circuit of the integrated circuit when the initialization signal is asserted and providing a second voltage to the digital circuit according to the control signal when the initialization signal is not asserted.

20. The process of claim 19 , further comprising:

reducing a variation of a voltage, due to at least one of manufacturing process, temperature, power supply voltage to the integrated circuit, using a load simulator.