On-chip service processor
View Patent ↗An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
1. An integrated circuit comprising:
one or more logic blocks to generate one or more system-operation signals at one or more system-operation clock rates; and
a service processor unit, said service processor unit comprising:
a control unit;
a buffer memory; and
a multiplicity of selectable probes,
wherein said service processor unit is adapted to perform capture and analysis of said system operation signals during normal system operation through said selectable probes.
2. The integrated circuit according to claim 1 , further comprising at least one port selected from the group consisting of:
a parallel I/O (PIO) port,
a serial I/O (SIO) port, and
a JTAG port;
wherein data and instructions are to be sent through at least one of said ports to said service processor unit from an external diagnostics console, and wherein result data is to be sent through at least one of said ports from said service processor unit to said external diagnostics console.
3. The integrated circuit according to claim 1 , wherein said selectable probes are selectable digital probes.
4. The integrated circuit according to claim 1 , wherein said selectable probes are selectable analog probes.
5. The integrated circuit according to claim 1 , wherein said service processor unit is adapted to perform debug operations of said integrated circuit.
6. The integrated circuit according to claim 1 , wherein said service processor unit is adapted to monitor said integrated circuit.
7. An integrated circuit comprising:
one or more logic blocks to generate one or more system-operation signals at one or more system-operation clock rates;
a system bus; and
a service processor unit, said service processor unit comprising:
a control unit;
a buffer memory; and
a system bus interface,
wherein said service processor unit is adapted to perform capture and analysis of system operation signals on said system bus during normal system operation through said system bus interface.
8. The integrated circuit according to claim 7 , further comprising at least one port selected from the group consisting of:
a parallel I/O (PIO) port,
a serial I/O (SIO) port, and
a JTAG port;
wherein data and instructions are to be sent through at least one of said ports to said service processor unit from an external diagnostics console, and wherein result data is to be sent through at least one of said ports from said service processor unit to said external diagnostics console.
9. The integrated circuit according to claim 7 , wherein said service processor unit is adapted to perform debug operations of said integrated circuit.
10. The integrated circuit according to claim 7 , wherein said service processor unit is adapted to monitor said integrated circuit.