System and method for sharing reset and background communication on a single MCU pin
Methods and data processing systems are provided to share a common pin between two circuits in microcontroller unit (MCU). Signals are received at a common pin included in the MCU. If the first circuit has been enabled, then the received signals are analyzed to determine whether the signals are valid command signals for the first circuit. If the signals are not a valid command signal, then a second circuit is performed. If the first circuit has not been enabled, then an alternate function is performed. One of the operations performed by the alternate function is to determine whether to enable the first function. In one embodiment, the first circuit is a background debug controller of the MCU and the second circuit is a reset circuit.
1. A computer-implemented method comprising:
receiving one or more signals at a common pin included in a microcontroller unit (MCU);
in response to determining that a first circuit has been enabled in the MCU:
analyzing the received signals;
in response to the analysis identifying a command encoded in the received signals, performing the command using the first circuit; and
in response to the analysis not identifying the command, performing a preset function using a second circuit; and
in response to determining that the first circuit has not been enabled at the MCU, performing an alternate function that includes attempting to synchronize the MCU with an external device over the common pin.
2. The method of claim 1 wherein the first circuit is a background debug controller, the command is a background debug command, the second circuit is a reset circuit, and the preset and alternate functions are a reset routine.
3. The method of claim 1 wherein performing the preset function further comprises:
driving the common pin for a first plurality of cycles;
after the driving, releasing the common pin for a second plurality of cycles;
in response to determining that the common pin is still being driven after the releasing, attempting to synchronize with an external device over the common pin; and
enabling the first circuit in response to successfully synchronizing with the external device.
4. The method of claim 1 wherein the first circuit is disabled in response to the analysis not identifying the command encoded in the received signals.
5. The method of claim 1 wherein, the alternate function further includes:
determining whether a hot connection is allowed at the MCU,
wherein the attempting to synchronize with the external device over the common pin is performed in response to determining that the hot connection is allowed; and
in response to successfully synchronizing with the external device, enabling the first circuit in response to receiving an enablement command from the external device within a preset number of cycles.
6. The method of claim 5 further comprising:
in response to determining that the hot connection is not allowed, performing the preset function, wherein the preset function is an MCU reset function;
performing the MCU reset function in response to an unsuccessful synchronization with the external device; and
performing the MCU reset function in response to not receiving the enablement command within the preset number of cycles.
7. The method of claim 5 wherein the first circuit is a background debug controller circuit and the second circuit is a reset circuit, the method further comprising:
after enabling the first circuit, receiving one or more background debug commands over the common pin; and
processing the background debug commands by the background debug controller circuit.
8. The method of claim 7 further comprising:
receiving a bad background debug signal after processing the background debug commands;
in response to receiving the bad background debug signal:
disabling the first circuit; and
resetting the MCU using the reset circuit.
9. A computer-implemented method comprising:
receiving, from an external device, one or more signals at a common pin included in a microcontroller unit (MCU) that includes a first and a second circuit, wherein the first circuit is initially disabled;
attempting to synchronize with the external device; and
in response to successfully synchronizing with the external device, enabling the first circuit in response to receiving an enablement command from the external device within a preset number of cycles, wherein the enablement command is encoded in one or more of the signals received from the external device at the common pin.
10. The method of claim 9 further comprising:
performing the second function in response to an unsuccessful synchronization with the external device, wherein the preset function is an MCU reset function; and
performing the MCU reset function in response to not receiving the enablement command within the preset number of cycles.
11. The method of claim 10 further comprising:
after enabling the first circuit, receiving one or more command signals at the common pin; and
processing, by the enabled first circuit, commands corresponding to the received command signals.
12. The method of claim 11 further comprising:
receiving a bad signal at the common pin after processing the command signals;
in response to receiving the bad signal:
disabling the first circuit; and
invoking the second circuit.
13. A data processing system comprising:
a processor used to execute a plurality of instructions;
a clock unit that sets one or more clock cycles;
a first circuit connected to the processor;
a second circuit connected to the processor;
a plurality of interface pins, wherein one of the interface pins is a common pin shared by the first and second circuits;
enablement circuitry that operates to enable processing of command signals received at the common pin by the first circuit when an external device, connected to the interface pins, is successfully synchronized with the data processing system; and
operation of the second circuit when signals are received at the common pin that are not processed by the first circuit.
14. The data processing system of claim 13 wherein the first circuit is a background debug controller circuit, the command signals correspond to background debug commands, and the second circuit is a reset circuit.
15. The data processing system of claim 13 wherein operation of the second circuit further comprises:
logic that drives the common pin for a first plurality of clock cycles;
after the driving, logic that releases the common pin for a second plurality of clock cycles;
synchronization logic that determines that the common pin is still low after the second plurality of clock cycles and attempts to synchronize with the external device over the common pin; and
enablement logic operated by the enablement circuitry that enables the first circuit in response to successfully synchronizing with the external device.
16. The data processing system of claim 13 wherein operation of the first circuit further comprises:
logic that disables the first circuit in response to receiving a bad command signal at the common pin.
17. The data processing system of claim 13 further comprising:
a register connected to the processor that includes a hot connection bit that indicates whether a hot connection is allowed by the data processing system;
hot connection logic that attempts to synchronize with the external device over the common pin when the hot connection bit is set; and
enablement logic operated by the enablement circuitry that enables the first circuit when an enablement command is received at the common pin within a preset number of clock cycles after the data processing system is successfully synchronized with the external device.
18. The data processing system of claim 17 further comprising:
logic to operate the second circuit when a signal is received at the common pin and the hot connection bit is not set;
logic to operate the second circuit in response to an unsuccessful synchronization between the data processing system and the external device; and
logic to operate the second circuit in response to not receiving the enablement command within the preset number of clock cycles.
19. The data processing system of claim 17 wherein the first circuit is a background debug controller circuit and the second circuit is a reset circuit, the microcontroller unit further comprising:
analysis logic that identifies a bad command signal received at the common pin after the external device is successfully synchronized with the data processing system; and
disablement logic that operates the second circuit and disables the first circuit in response to identifying the bad command signal.
20. The data processing system of claim 19 wherein the external device is a pod and wherein the number of interface pins is less than or equal to 8.