Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable, in-memory processing semiconductor device

1. A method for specifying stateful, transaction-oriented systems for configuring one of a programmable hardware array or programmable processor array through a FlowLogic language, comprising method operations of:

designating a plurality of primitive FlowModules;

defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interuptable sequence of procedure code, a single point of entry and is invoked by a named concurrent call;

encapsulating one of the primitive FlowModules or a HierarchicalFlowModule into another HierarchicalFlowModule, wherein the another HierarchicalFlowModule includes input ports for every intersected incoming arc and output ports for every intersected outgoing arc;

designating an Arc from a calling FlowGate to a called FlowGate, the designating including designating an Arc pair as a CallForwardArc and a ForwardArc, wherein the ForwardArc does not have an explicit destination FlowGate name on invocation, and the CallForwardArc explicitly specifies the destination FlowGate of the resulting ForwardArc;

generating a Signal for each named invocation of the called FlowGate;

defining a Channel for carrying the Signal; and

compiling the HierarchicalFlowModule for configuring one of the programmable hardware array or the programmable processor array.

2. The method of claim 1 wherein each FlowGate includes local state variables and each FlowGate has a short lifetime.

3. The method of claim 1 , wherein each FlowGate does not include any dynamically allocated heap variables and has no post termination state.

4. The method of claim 1 , wherein each FlowGate is capable of being executed concurrently with other FlowGates of other primitive FlowModules.

5. The method of claim 1 , wherein each FlowGate is enabled to make concurrent calls to other FlowGates and itself.

6. The method of claim 1 , wherein only one FlowGate executes at a time per primitive FlowModule.

7. The method of claim 1 , wherein the Signal is delivered asynchronously to the called FlowGate on a first in first out basis.

8. The method of claim 1 , wherein Signals generated by multiple source FlowGates for one of a same destination FlowGate or a different destination FlowGate within the same FlowModule are associated with a non-deterministic order.

9. The method of claim 1 , further comprising:

classifying the Signal into a class; and

assigning each class to a different Channel.

10. The method of claim 9 , wherein classifying the Signal includes,

assigning priorities to the Signal, wherein a Channel having higher priority Signal is assigned more resources.

11. The method of claim 1 , wherein each Signal addresses the called FlowGate and has a variable size.

12. The method of claim 1 , wherein the Primitive FlowModule is an object containing an object oriented FlowMethod.

13. The method of claim 12 , wherein the object oriented FlowMethod is invoked by one of FlowGates or a FlowMethod within a same FlowModule.

14. The method of claim 13 , wherein the FlowMethod is unable to call itself and wherein the FlowMethod has no post-termination persistent states.

15. The method of claim 12 , wherein local state variables last a lifetime of the FlowMethod.

16. The method of claim 12 , wherein there does not exist any dynamically allocated heap local variables.

17. The method of claim 12 , wherein a sequence of procedural code is non-interruptable.

18. The method of claim 1 , wherein each of the primitive FlowModules includes a set of static variables defining possible states.

19. The method of claim 18 , wherein the possible states are accessible by one of the at least one FlowGate or a FlowMethod of the FlowModule.

20. The method of claim 1 further comprising:

designating a destination DynamicFlowGate, the destination DynamicFlowGate enabling a source FlowGate to supply execution code for a destination FlowGate.

21. The method of claim 1 , further comprising

designating a FlowTunnel, wherein the sub-design, and is associated with a larger FlowLogic Design, with two or more Clusters, the Clusters exchanging specially attributed Signals routed through the FlowTunnel.

22. The method of claim 21 , wherein the FlowTunnel enables abstract mapping of an underlying physical communications layer.

23. The method of claim 21 , wherein the clusters are compiled into sequential code for mapping into uniprocessor sub-systems, which includes driver software running on a host machine.

24. A method for specifying stateful, transaction-oriented systems for configuring one of a programmable hardware array or programmable processor array through a FlowLogic language, comprising method operations of:

designating a plurality of primitive FlowModules;

defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptable sequence of procedure code, a single point of entry and is invoked by a named concurrent call;

designating an Arc from a calling FlowGate to a called FlowGate

generating a Signal for each named invocation of the called FlowGate, the designating the Arc and generating the Signal including,

designating a TimedArc from the calling FlowGate to the called FlowGate;

carrying a TimerSignal in a TimerChannel; and,

delivering the TimerSignal in an order of time expiration relative to other TimerSignals, the designating including designating an Arc pair as a CallForwardArc and a ForwardArc, wherein the ForwardArc does not have an explicit destination FlowGate name on invocation, and the CallForwardArc explicitly specifies the destination FlowGate of the resulting ForwardArc;

defining a Channel for carrying the Signal; and

compiling the FlowModules for configuring one of the programmable hardware array or the programmable processor array.

25. A method for specifying stateful, transaction-oriented systems for configuring one of a programmable hardware array or programmable processor array through a FlowLogic language, comprising method operations of:

designating a plurality of primitive FlowModules;

defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interuptable sequence of procedure code, a single point of entry and is invoked by a named concurrent call;

designating an Arc from a calling FlowGate to a called FlowGate, the designating including,

designating an Arc pair as a CallForwardArc and a ForwardArc, wherein the ForwardArc does not have an explicit destination FlowGate name on invocation, and the CallForwardArc explicitly specifies the destination FlowGate of the resulting ForwardArc;

generating a Signal for each named invocation of the called FlowGate;

defining a Channel for carrying the Signal; and

compiling the FlowModules for configuring one of the programmable hardware array or the programmable processor array.