Data-level clock recovery
A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.
1. An integrated circuit device comprising:
a first sampling circuit to generate a sequence of data samples in response to a first clock signal, each data sample in the sequence of data samples having one of at least two states according to whether an incoming signal exceeds a first threshold; and
data-level crossing logic to determine whether the sequence of data samples matches a pattern that corresponds to a sloped input-signal crossing of the first threshold.
2. The integrated circuit device of claim 1 further comprising a second sampling circuit to generate a sequence of error samples in response to the first clock signal, each error sample in the sequence of error samples having one of at least two states according to whether the incoming signal exceeds a second threshold.
3. The integrated circuit device of claim 2 wherein the data-level crossing logic includes circuitry to generate, in response to a determination that the sequence of data samples matches the pattern, a first early/late signal that indicates whether a transition of the first clock signal occurred before or after the sloped-input-signal crossing of the first threshold based on at least one of the first clock signal, at least one of the error samples, or at least one of the data samples.
4. The integrated circuit device of claim 3 wherein the circuitry to generate the first early/late signal includes a first logic to generate the first early/late signal in either a first logic state or a second logic state according to whether at least one of the error samples is captured before or after the sloped input-signal crossing of the first threshold.
5. The integrated circuit device of claim 3 further comprising a first phase adjust circuit to adjust the phase of the first clock signal based, at least in part, on the first early/late signal.
6. The integrated circuit device of claim 5 wherein the first phase adjust circuit comprises a counter to update a count value in response to the first early/late signal.
7. The integrated circuit device of claim 6 wherein the first phase adjust circuit includes logic to generate a first phase-adjust signal based, at least in part, on the count value.
8. The integrated circuit device of claim 7 wherein the logic to generate the first phase-adjust signal comprises a majority-detect circuit to generate the first phase-adjust signal based, at least in part, on whether a majority of early/late signals, within a set of early/late signals that includes the first early-late signal, indicate that the first clock signal is transitioning early or late relative to sloped input-signal crossings of the first threshold.
9. The integrated circuit device of claim 7 wherein the first phase-adjust signal comprises multiple bits.
10. The integrated circuit device of claim 7 wherein the logic to generate the first phase-adjust signal comprises a first circuit to generate the first phase-adjust signal in one of at least two logic states according to whether the count value exceeds a predetermined count.
11. The integrated circuit device of claim 10 further comprising a second circuit to store the predetermined count, wherein the second circuit is a programmable storage circuit.
12. The integrated circuit device of claim 7 wherein the logic to generate the first phase-adjust signal comprises circuitry to update the first phase-adjust signal at a first update rate.
13. The integrated circuit device of claim 12 further comprising data-state transition logic to determine whether a second clock signal is transitioning early or late relative to at least a transition in the incoming signal.
14. The integrated circuit device of claim 13 wherein the second clock signal has a predetermined phase offset relative to the first clock signal.
15. The integrated circuit device of claim 14 wherein the predetermined phase offset is determined, at least in part, on the first phase-adjust signal.
16. The integrated circuit device of claim 13 further comprising a second phase adjust circuit to generate a second phase-adjust signal based, at least in part, on at least a zero-crossing of the incoming signal.
17. The integrated circuit device of claim 16 wherein the second phase adjust circuit comprises logic to update the second phase-adjust signal at a second update rate.
18. The integrated circuit device of claim 17 wherein the first update rate of the first phase-adjust signal and the second update rate of the second phase-adjust signal establish a desired update ratio.
19. The integrated circuit device of claim 18 further comprising a clock generation circuitry to generate the first clock signal and the second clock signal with a phase offset relative to each other based, at least in part, on the first phase-adjust signal and the second phase-adjust signal.
20. A method of operation within an integrated circuit device, the method comprising:
generating a sequence of data samples in response to a first clock signal, each data sample in the sequence of data samples having one of at least two states according to whether an incoming signal exceeds a first threshold; and
determining whether the sequence of data samples matches a pattern that corresponds to a sloped input-signal crossing of the first threshold.
21. The method of claim 20 further comprising generating a sequence of error samples in response to the first clock signal, each error sample in the sequence of error samples having one of at least two states according to whether the incoming signal exceeds a second threshold.
22. The method of claim 21 further comprising generating, in response to a determination that the sequence of data samples matches the pattern, a first early/late signal that indicates whether a transition of the first clock signal occurred before or after the sloped-input-signal crossing of the first threshold based on at least one of the first clock signal, at least one of the error samples or at least one of the data samples.
23. The method of claim 22 wherein generating the first early/late signal comprises generating the first early/late signal in either a first logic state or a second logic state according to whether at least one of the error samples is captured before or after the sloped input-signal crossing of the first threshold.
24. The method of claim 22 further comprising adjusting the phase of the first clock signal based, at least in part, on the first early/late signal.
25. The method of claim 24 wherein adjusting the phase of the first clock signal comprises generating a phase-adjust signal based, at least in part, on whether a majority of first early/late signals, within a set of first early/late signals that includes the first early/late signal, indicate that the first clock signal is transitioning early or late relative to sloped input-signal crossings of the first threshold.
26. An integrated circuit device comprising:
means for generating a sequence of data samples in response to a first clock signal, each data sample in the sequence of data samples having one of at least two states according to whether an incoming signal exceeds a first threshold; and
means for determining whether the sequence of data samples matches a pattern that corresponds to a sloped input-signal crossing of the first threshold.