Quadrature divider
The quadrature divider comprises a plurality of flip-flops, including at least a first flip flop and an endmost flip-flop, interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes differential inputs, differential outputs and differential clock inputs, the outputs of one flip-flop are connected to the corresponding inputs of a subsequent flip-flop, the outputs of the endmost flip-flop are connected inversely to the inputs of the first flip-flop, wherein the flip-flops are clocked at their clock inputs with differential clock signals in a consecutive manner which, for each flip-flop and depending on the dividing ratio, are individually selected from quadrature clock input signals.
1. A quadrature divider, comprising
a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, wherein the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,Ī, two differential outputs O,Ō and two differential clock inputs C, C , the outputs O,Ō of one flip-flop are connected to the corresponding inputs I,Ī of a subsequent flip-flop, the outputs O,Ō of the endmost flip-flop are connected inversely to the inputs I,Ī of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, C with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_ 0 , In_ 90 , In_ 180 , and In_ 270 , wherein the quadrature divider is an even number divide-by-n circuit comprising a number of 2n flip-flops and providing a number of 4n output signals having 4n equidistant phases.
2. The quadrature divider of claim 1 , wherein the clock inputs C, C of the n-th flip-flop are connected to the clock input signals In 0 +(n−1)*90 and In 180 +(n−1)*90, respectively.
3. The quadrature divider of claim 1 , which comprises flip-flop circuits which are set by a clock input and reset by an inverted clock input.
4. The quadrature divider of claim 1 , which comprises flip-flop circuits which are set by a clock input and reset by an inverted clock input.
5. The quadrature divider of claim 3 , wherein the quadrature divider is an odd number divide-by-n circuit comprising a number of 2n flip-flops and providing a number of 4n output signals having 4n equidistant phases.
6. The quadrature divider of claim 4 , wherein a prime number division factor n is determined by applying a certain clock input phase to each of the consecutive flip-flops.
7. A quadrature divider, comprising a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, wherein the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,Ī, two differential outputs O,Ō and two differential clock inputs C, C , the outputs O,Ō of one flip-flop are connected to the corresponding inputs I,Ī of a subsequent flip-flop, the outputs O,Ō of the endmost flip-flop are connected inversely to the inputs I,Ī of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, C with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_ 0 , In_ 90 , In_ 180 , and In_ 270 , wherein the quadrature divider is an odd number divide-by-n circuit comprising a number of 2n flip-flops and providing a number of 4n output signals having 4n equidistant phases.
8. The quadrature divider of claim 7 , wherein the clock inputs C, C of the n-th flip-flop are connected to the clock input signals In_ 0 +(n−1)*270 and In_ 180 +(n−1)*270, respectively.
9. The quadrature divider of claim 7 , which comprises flip-flop circuits which are set by a clock input and reset by an inverted clock input.
10. A quadrature divider, comprising a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, wherein the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,Ī, two differential outputs O,Ō and two differential clock inputs C, C the outputs O,Ō of one flip-flop are connected to the corresponding inputs I,Ī of a subsequent flip-flop, the outputs O,Ō of the endmost flip-flop are connected inversely to the inputs I,Ī of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, C with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals. In_ 0 , In_ 90 , In_ 180 , and In_ 270 , wherein the quadrature divider is an odd number divide-by-3n circuit comprising a number of 2n flip-flops and providing a number of 4n output signals having 4n equidistant phases.
11. The quadrature divider of claim 10 , wherein the clock inputs C, C of the n-th flip-flop are connected to the clock input signals In_ 0 +(n−1)*270 and In_ 180 +(n−1)*270, respectively.
12. A quadrature divider, comprising a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, wherein the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,Ī, two differential outputs O,Ō and two differential clock inputs C, C the outputs O,Ō of one flip-flop are connected to the corresponding inputs I,Ī of a subsequent flip-flop, the outputs O,Ō of the endmost flip-flop are connected inversely to the inputs I,Ī of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, C with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_ 0 , In_ 90 , In_ 180 , and In_ 270 , wherein the quadrature divider is a prime number divide-by-n circuit, where n>=5, comprising a number of n−1 flip-flops, and providing a number of 2n output signals with at least quadrature output phases of 0°, 90°, 180°, and 270°.
13. The quadrature divider of claim 12 , wherein a prime number division factor n is determined by applying a certain clock input phase to each of the consecutive flip-flops.
14. The quadrature divider of claim 12 , which comprises flip-flop circuits which are set by a clock input and reset by an inverted clock input.
15. A quadrature divider, comprising a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, wherein the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,Ī, two differential outputs O,Ō and two differential clock inputs C, C , the outputs O,Ō of one flip-flop are connected to the corresponding inputs I,Ī of a subsequent flip-flop, the outputs O,Ō of the endmost flip-flop are connected inversely to the inputs I,Ī of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, C with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_ 0 , In_ 90 , In_ 180 , and In_ 270 , wherein the quadrature divider is an odd number divide-by-3n circuit comprising a number of 2n flip-flops and providing a number of 4n output signals having 4n equidistant phases, and wherein the quadrature divider includes flip-flop circuits which are set by a clock input and reset by an inverted clock input.