Semiconductor integrated circuit and nonvolatile memory element
View Patent ↗A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.
1. A semiconductor integrated circuit device on a semiconductor substrate, comprising:
a plurality of word lines;
a plurality of data lines; and
a plurality of electrically programmable and erasable non-volatile memory cells coupled to the plurality of word lines and to the plurality of data lines so that each electrically programmable and erasable non-volatile memory cell is coupled to one of the word lines and to one of the data lines, each electrically programmable and erasable non-volatile memory cell comprising:
a MIS transistor including a first gate comprised of a first level polycrystalline silicon layer, a second gate comprised of a semiconductor region in the semiconductor substrate, the second gate being coupled to the corresponding word line, a source, and a drain coupled to the corresponding data line.
2. A semiconductor integrated circuit device according to claim 1 , further comprising:
a volatile memory coupled to receive data stored in at least one of the electrically programmable and erasable non-volatile memory cells.
3. A semiconductor integrated circuit device on a semiconductor substrate, comprising:
a plurality of word lines;
a plurality of data lines; and
a plurality of electrically programmable and erasable non-volatile memory cells coupled to the plurality of word lines and to the plurality of data lines so that each electrically programmable and erasable non-volatile memory cell is coupled to one of the word lines and to one of the data lines, each electrically programmable and erasable non-volatile memory cell comprising a pair of memory elements each of which includes:
a MIS transistor including a first gate comprised of a first level polycrystalline silicon layer, a second gate comprised of a semiconductor region in the semiconductor substrate, the second gate being coupled to the corresponding word line, a source, and a drain coupled to the corresponding data line.
4. A semiconductor integrated circuit device according to claim 3 , further comprising:
a volatile memory coupled to receive data stored in at least one of the electrically programmable and erasable non-volatile memory cells.