Method of fabricating CMOS inverters and integrated circuits utilizing strained surface channel MOSFETs
A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si 1-x Ge x layer on the Si substrate, and a strained surface layer on said relaxed Si 1-x Ge x layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si 1-x Ge x layer on the Si substrate, and a strained layer on the relaxed Si 1-x Ge x layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor interconnected in a CMOS circuit.
1 - 62 . (canceled)
63 . A method of fabricating a circuit comprising the steps of:
providing a structure comprising a substrate, the structure having a surface roughness of less than 1 nm;
adding a strain-inducing material to the structure, the strain-inducing material consisting essentially of SiGe; and
integrating a pMOSFET and an nMOSFET in the structure,
wherein a channel of the pMOSFET and a channel of the nMOSFET are each strained and the strain in at least one of the strained channels is induced by the strain-inducing material.
64 . The method of claim 63 , wherein at least one of the pMOSFET and nMOSFET channels consists essentially of silicon.
65 . The method of claim 64 , wherein the pMOSFET channel and the nMOSFET channel each consist essentially of silicon.
66 . The method of claim 65 , wherein the pMOSFET and nMOSFET are interconnected to form an inverter.
67 . The method of claim 63 , wherein the structure further comprises an insulator layer disposed over the substrate and at least one of the strained channels is disposed over the insulator layer.
68 . The method of claim 67 , wherein at least one of the pMOSFET and nMOSFET channels consists essentially of silicon.
69 . The method of claim 68 , wherein the pMOSFET channel and the nMOSFET channel each consist essentially of silicon.
70 . The method of claim 69 , wherein the pMOSFET and nMOSFET are interconnected to form an inverter.
71 . The method of claim 67 , wherein both of the strained channels are disposed over the insulator layer.
72 . The method of claim 63 , wherein the strain-inducing material is at least partially relaxed.
73 . A method of fabricating a circuit comprising the steps of:
providing a structure comprising a substrate, the structure having a surface roughness of less than 1 nm;
adding a strain-inducing material to the structure; and
integrating a pMOSFET and an nMOSFET in the structure,
wherein a channel of the pMOSFET and a channel of the nMOSFET are each strained and consists essentially of silicon, and the strain in at least one of the strained channels is induced by the strain-inducing material.