IP Library Granted Patent US 7,482,832
Granted Patent B2
US 7,482,832 · App. 11/434,715 · Granted Jan 27, 2009

Termination circuit and semiconductor device comprising that termination circuit

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Quick Facts
Patent No.
US 7,482,832
App. No.
11/434,715
Granted
Jan 27, 2009
Kind
B2
Abstract

A termination circuit that adjusts differences in the resistance values of wiring-layer resistance and transistor ON resistance so that a desired termination resistance value is obtained. A wiring-layer resistance 10 is connected between an input terminal 30 , which connects to an input circuit 18 , and a first node; a transistor group 12 is connected between the first node and ground; a wiring-layer resistance 11 is connected between the first node and a second node; and a transistor group 13 is connected between the second node and ground. Furthermore, a wiring-layer resistance 14 is connected between the input terminal 30 and a third node; a transistor group 16 is connected between the third node and power source VDD; a wiring-layer resistance 15 is connected between the third node and a fourth node, and a transistor group 17 is connected between a fourth node and power source VDD. The transistor groups 12, 13, 16, 17 comprise one or a plurality of transistors that are turned ON or OFF by respective control signals BN 1 to BN 4 , BN 5 to BN 8 , BP 1 to BP 4 and BP 5 to BP 8.

Claims (20)

1. A termination circuit, comprising:

a first resistance element that is connected between an input terminal, which connects to an input circuit, and a first node;

a first switch group that is connected between said first node and a first power source, said first switch group adjusting resistance value between the first node and the first power source;

a second resistance element that is connected between said first node and a second node;

a second switch group that is connected between said second node and said first power source, said second switch group adjusting resistance value between the second node and the first power source;

a third resistance element that is connected between said input terminal and a third node;

a third switch group that is connected between said third node and a second power source;

a fourth resistance element that is connected between said third node and a fourth node; and

a fourth switch group that is connected between said fourth node and said second power source.

2. The termination circuit of claim 1 wherein each of said first to fourth resistance elements are wiring-layer resistances.

3. A semiconductor apparatus that comprises the termination circuit of claim 2 .

4. The termination circuit of claim 1 wherein each of said first to fourth switch groups comprise one or a plurality of transistors that are turned ON or OFF by respective control signals.

5. A semiconductor apparatus that comprises the termination circuit of claim 4 .

6. The termination circuit of claim 4 wherein sources of the plurality of transistors are common and connected either to the first power source or the second power source.

7. The termination circuit of claim 4 wherein drains of the plurality of transistors are common and connected to the respective first to fourth resistance elements.

8. The termination circuit of claim 4 wherein gates of the plurality of transistors supply the respective control signals.

9. The termination circuit of claim 4 wherein the plurality of transistors are connected in parallel.

10. The termination circuit of claim 1 wherein said input terminal is an input/output terminal that is further connected to an output circuit.

11. A semiconductor apparatus that comprises the termination circuit of claim 5 .

12. A semiconductor apparatus that comprises the termination circuit of claim 1 .

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046867/0248 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032899/0588 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2006
From: KOSHITA, GEN
To: ELPIDA MEMORY, INC.
Reel/Frame 017886/0248 →