Interface circuit for data transmission and method thereof

1. An interface circuit whereby data is transmitted through first data signals during a first data period, a second data period, and a third data period respectively corresponding to a first rising, a first falling edge, and a second rising edge of a clock signal, wherein the first data period, the second data period, and the third data period are continuous, the second data period follows the first period, and the third data period follows the second data period, the interface circuit comprising:

a transition detection unit for selectively asserting a first detection signal, of which a constant level of the first detection signal lasts longer than a ½ cycle of the clock signal, in response to the number of the first data signals having transitions between the first data period and the second data period, and selectively asserting a second detection signal, of which a constant level of the first detection signal lasts longer than a ½ cycle of the clock signal, in response to the number of the first data signals having transitions between the second data period and the third data period; and

a transition reduction unit for generating second data signals by outputting the inverted and non-inverted first data signals respectively when the first detection signal or the second detection signal is asserted and de-asserted.

2. The interface circuit as claimed in claim 1 , wherein the first detection signal or the second detection signal is asserted when the number of the first data signals having transitions is greater than a threshold.

3. The interface circuit as claimed in claim 2 , wherein the threshold is half of the number of the first data signals.

4. An interface circuit comprising:

a transmitter for providing data through first data signals during a first data period, a second data period and a third data period respectively corresponding to a first rising edge, a first falling edge, and a second rising edge of a clock signal, wherein the first data period, the second data period, and the third data period are continuous, the second data period follows the first period, and the third data period follows the second data period;

a transition detection unit for selectively asserting a first detection signal, of which a constant level lasts longer than a ½ cycle of the clock signal, in response to the number of the first data signals having transitions between the first data period and the second data period, and selectively asserting a second detection signal, of which a constant level of the second detection signal lasts longer than a ½ cycle of the clock signal, in response to the number of the first data signals having transitions between the second data period and the third data period;

a transition reduction unit for generating second data signals by outputting the inverted and non-inverted first data signals respectively when the first detection signal or the second detection signal is asserted and de-asserted; and

a receiver for restoring the data from the second data signals using the first detection signal and second detection signal.

5. The interface circuit as claimed in claim 4 , wherein the data is transmitted from a timing controller to a source driver of an LCD.

6. The interface circuit as claimed in claim 4 , wherein the first detection signal or the second detection signal is asserted when the number of the first data signals having transitions is greater than a threshold.

7. The interface circuit as claimed in claim 6 , wherein the threshold is half of the number of the first data signals.

8. The interface circuit as claimed in claim 4 , wherein the data restored by the receiver is substantially the same as the data provided by the transmitter.

9. The interface circuit as claimed in claim 4 , wherein the transmitter and the receiver are located in a timing controller and a source driver of an LCD respectively.