IP Library Granted Patent US 7,601,996
Granted Patent B2
US 7,601,996 · App. 11/438,684 · Granted Oct 13, 2009

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 7,601,996
App. No.
11/438,684
Granted
Oct 13, 2009
Kind
B2
Abstract

A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.

Claims (14)

1. A semiconductor device including a field-effect transistor arranged in a semiconductor substrate, the transistor comprising:

a gate electrode;

a source/drain extension region in the semiconductor substrate;

a source/drain impurity diffusion region in the semiconductor substrate deeper than the source/drain extension region;

a carbon layer surrounding the source/drain impurity diffusion region; and

a pocket region located below the source/drain extension region,

wherein the carbon layer is offset from front edges of the source/drain extension region and the pocket region in the direction away from the gate electrode.

2. The semiconductor device according to claim 1 , wherein the source/drain impurity diffusion region is offset from a channel-side boundary of the carbon layer so as to be away from the gate electrode.

3. The semiconductor device according to claim 1 , wherein the carbon layer is positioned deeper in the semiconductor substrate than a bottom of the source/drain impurity diffusion region.

4. The semiconductor device according to claim 1 , further comprising:

a first sidewall spacer provided on a side face of the gate electrode; and

a second sidewall spacer covering the first sidewall spacer;

wherein the channel-side boundary of the carbon layer aligns with the first sidewall spacer, and the source/drain impurity diffusion region aligns with the second sidewall spacer.

5. The semiconductor device according to claim 1 , wherein at least a part of the source/drain extension region extends outside the carbon layer.

Assignments (4)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2006
From: OHTA, HIROYUKI; OKABE, KENICHI
To: FUJITSU LIMITED
Reel/Frame 018101/0092 →