Loop filter integration in phase-locked loops

1. A semiconductor chip, comprising: a phase-locked loop including:

a charge pump system comprising a first charge pump and a second charge pump configured to provide control signals comprising a first control signal and a second control signal, respectively, wherein the first control signal increases or decreases in magnitude concurrently with the second control signal; and

a dual-path filter, the dual-path filter consisting of passive components that are configured to provide summation of the control signals, the dual-path filter further including a first node coupled between the first charge pump and a first capacitor and a second node coupled to the second charge pump through a first resistor, the second node also being connected to the first capacitor.

2. The chip of claim 1 , further comprising a voltage source coupled to the second node through a second resistor.

3. The chip of claim 2 , further comprising a third node coupled between the voltage source and the second resistor.

4. The chip of claim 3 , further comprising a second capacitor coupled between the first capacitor and the third node.

5. The chip of claim 4 , further comprising a third capacitor coupled between ground and the first resistor.

6. The chip of claim 1 , further comprising an oscillator coupled to a single output connection corresponding to the dual-path filter, the single output connection configured to carry the summed control signals.

7. The chip of claim 1 , further comprising an oscillator coupled to the dual-path filter, a detector coupled to the charge pump system, and a mixer or divide-by-N module coupled between the detector and the oscillator.

8. A method of operating a phase-locked loop, comprising:

providing control signals comprising first and second control signals to a dual-path filter, the first control signal increasing or decreasing in magnitude concurrently with the second control signal; and

at the dual-path filter: providing the first control signal to an integrator path and providing the second control signal at a low pass filter path; and summing the control signals corresponding to the integrator path and the low pass filter path, wherein the integrator path comprises a first resistor, a series capacitance arrangement, and a first node disposed between the first resistor and the series capacitance arrangement, wherein the low pass filter path comprises a second resistor, a third resistor, and a second node disposed between the second and third resistor, and a capacitor in parallel with the second and third resistor.

9. The method of claim 8 , wherein providing the first control signal comprises providing a current signal of lesser magnitude than the second control signal.

10. The method of claim 8 , wherein summing comprises connecting the third resistor to a capacitor of the series capacitance arrangement at the second node to provide a summed output signal at the first node.