Method for manufacturing semiconductor device
View Patent ↗A method for manufacturing a semiconductor device comprises forming a laser marking, forming a trench pattern, forming a metal interconnection layer, removing a predetermined portion of the metal interconnection layer, and planarizing the metal interconnection layer. The laser marking is formed in a first region of a wafer, and the first region has a first width from an edge of the wafer. The trench pattern is formed above the wafer except for above the first region. The metal interconnection layer is formed above the wafer where the laser marking and the trench pattern are formed. The predetermined portion of the metal interconnection layer is removed, and the predetermined portion has a second width from the edge of the wafer equal to or greater than the first width. And the metal interconnection layer above the wafer where the trench pattern is formed is planarized to a predetermined thickness.
1. A method for manufacturing a semiconductor device, comprising:
forming a laser marking in a first region of a wafer, the first region having a first width from an edge of the wafer;
forming a trench pattern above the wafer except for above the first region;
forming a metal interconnection layer above the wafer where the laser marking and the trench pattern are formed;
removing a predetermined portion of the metal interconnection layer, the predetermined portion having a second width from the edge of the wafer equal to or greater than the first width; and
planarizing the metal interconnection layer above the wafer where the trench pattern is formed to a predetermined thickness,
wherein the metal interconnection layer is formed of at least one material selected from the group consisting of Al, Al-alloy, Cu, Au, Ag, W, and Mo.
2. The method according to claim 1 , wherein the first width is in a range of about 2.5 mm -3.0 mm from the edge of the wafer.
3. The method according to claim 1 , wherein the laser marking is formed in a region where the first width and the second width overlap each other.
4. The method according to claim 1 , wherein the first width is less than about 2.5 mm from the edge of the wafer.
5. The method according to claim 1 , wherein the second width is equal to or greater than the first width and does not reach the region where the trench pattern is formed.
6. The method according to claim 1 , wherein the removing a predetermined portion of the metal interconnection layer is accomplished by over-etching of over about 200%.
7. A method for manufacturing a semiconductor device, comprising:
forming a laser marking in a first region of a wafer, the first region having a first width from an edge of the wafer;
forming a trench pattern above the wafer except for above the first region;
forming a metal interconnection layer above the wafer where the laser marking and the trench pattern are formed;
removing a predetermined portion of the metal interconnection layer, the predetermined portion having a second width from the edge of the wafer equal to or greater than the first width; and
planarizing the metal interconnection layer above the wafer where the trench pattern is formed to a predetermined thickness, wherein planarizing the metal interconnection layer is accomplished by a chemical mechanical polishing (CMP) process.
8. A method for manufacturing a semiconductor device, comprising:
forming a laser marking in a first region of a wafer, the first region having a first width from an edge of the wafer;
forming a trench pattern above the wafer except for above the first region;
forming a metal interconnection layer above the wafer where the laser marking and the trench pattern are formed;
removing a predetermined portion of the metal interconnection layer, the predetermined portion having a second width from the edge of the wafer equal to or greater than the first width; and
planarizing the metal interconnection layer above the wafer where the trench pattern is formed to a predetermined thickness,
wherein forming the metal interconnection layer is accomplished by using at least one process selected from the group consisting of a reflowing of a conductive material formed by sputtering, a chemical vapor deposition (CVD) process, and an electroplating process.
9. The method according to claim 8 , further comprising forming a seed layer to make a current flow during electrolysis when the electroplating process is used.
10. A method for manufacturing a semiconductor device, comprising:
forming a laser marking in a first region of a wafer, the first region having a first width from an edge of the wafer;
forming a trench pattern above the wafer except for above the first region;
forming a diffusion barrier layer on the trench pattern;
forming a metal interconnection layer above the wafer where the laser marking, the trench pattern, and the diffusion barrier layer are formed;
removing a predetermined portion of the metal interconnection layer, the predetermined portion having a second width from the edge of the wafer equal to or greater than the first width; and
planarizing the metal interconnection layer above the wafer where the trench pattern is formed to a predetermined thickness.
11. The method according to claim 10 , wherein the diffusion barrier layer is formed of at least one material selected from the group consisting of Ta, TaN, TiN, WN, TaC, WC, TiSiN, and TaSiN.
12. The method according to claim 10 , wherein forming the diffusion barrier layer is accomplished by using at least one process selected from the group consisting of a physical vapor deposition (PVD) process, and an atomic layer deposition (ALD) process.