Method for fabricating CMOS image sensor
View Patent ↗A method for fabricating a CMOS image sensor is provided. The method includes: forming a gate electrode with a gate insulating layer interposed on a transistor region of a semiconductor substrate having an active region defined by a photo diode and a transistor region; forming a first impurity region of a first conductive type at a transistor region at one side of the gate electrode; forming a second impurity region of a first conductive type at a photo diode region at other side of the gate electrode; forming sidewall insulating layers at both sides of the gate electrode; forming a third impurity region of a first conductive type at one side of a gate electrode where the first impurity region is formed; and forming a fourth impurity region of a second conductive type at the gate electrode, the photodiode region and the transistor region by implanting impurity ions of a second conductive type on the entire surface of the semiconductor substrate.
1. A method for fabricating a CMOS image sensor comprising:
forming a gate electrode with a gate insulating layer interposed on a transistor region of a semiconductor substrate having an active region defined by a photodiode and the transistor region;
forming a first impurity region of a first conductive type at the transistor region at a first side of the gate electrode;
forming a second impurity region of the first conductive type at the photodiode region at a second side of the gate electrode;
forming sidewalls comprising a first insulating layer and a second insulating layer at the first side and the second side of the gate electrode;
forming a third impurity region of the first conductive type at the first side of the gate electrode where the first impurity region is formed; and
forming a fourth impurity region of a second conductive type by implanting impurity ions of a second conductive type into the gate electrode, the photodiode region including the second impurity region, and the transistor region using the sidewalls as a hard mask.
2. The method according to claim 1 , wherein the second impurity region is formed deeper in the substrate than the first impurity region.
3. The method according to claim 1 , further comprising forming 60 Å and less of an oxide layer on a top and side surfaces of the gate electrode.
4. The method according to claim 1 , wherein forming the first impurity region comprises forming a lightly doped n− type diffusion region by implanting impurity ions of an n type at the transistor region.
5. The method according to claim 1 , wherein forming the second impurity region comprises forming a lightly doped n− type diffusion region by implanting impurity ions of an n type into the photodiode region at an ion implanting energy of 100 KeV to 500 KeV.
6. The method according to claim 1 , wherein forming the third impurity region comprises forming a n+ type diffusion region by implanting impurity ions of the n type at the transistor region of the substrate.
7. The method according to claim 1 , wherein forming the fourth impurity region comprises forming a P o diffusion region on the second impurity region and the third impurity region by implanting P o impurity ions into the entire substrate using the sidewalls as a hard mask.
8. The method according to claim 1 , wherein forming the fourth impurity region comprises forming a P o diffusion region on the second impurity region, the third impurity region, and the gate electrode by implanting P o impurity ion into the entire substrate using the sidewalls as a hard mask.
9. The method according to claim 1 , wherein the impurity ions of the second conductive type are BF 2 .
10. The method according to claim 9 , wherein the implantation dose of the BF 2 ion is 1×10 11 atoms/cm 2 to 5×10 12 atoms/cm 2 .
11. The method according to claim 9 , wherein the ion implanting energy is about 40 KeV and less for implanting the BF 2 ions.
12. The method according to claim 9 , wherein the dopant concentration of the fourth impurity region is 1×10 16 atoms/cm 3 to 5×10 17 atoms/cm 3 .
13. The method according to claim 1 , wherein the impurity ions of the second conductive type are boron.
14. The method according to claim 13 , wherein the implantation dose of the boron ion is 1×10 11 atoms/cm 2 to 5×10 12 atoms/cm 2 .
15. The method according to claim 13 , wherein ion implanting energy is 10 KeV and less for implanting the boron ions.
16. The method according to claim 13 , wherein the dopant concentration of the fourth impurity region is 1×10 16 atoms/cm 3 to 5×10 17 atoms/cm 3 .
17. The method according to claim 1 , further comprising performing a thermal process on the substrate after forming the fourth impurity region.
18. The method according to claim 1 , wherein the first insulating layer is 150 Å to 250 Å and the second insulating layer is 700 Å to 900 Å.
19. The method according to claim 1 , wherein forming the sidewalls comprises:
sequentially depositing the first insulating layer and the second insulating layer; and
performing an etch-back process on the first insulating layer and the second insulating layer.
20. The method according to claim 1 , further comprising forming an oxide layer on the gate electrode of about 60 Å and less.