Method for fabricating CMOS image sensor

1. A method of fabricating a CMOS image sensor comprising:

forming a gate electrode with a gate insulating layer interposed at a transistor region of a semiconductor substrate having an active region defined by a photodiode region and a transistor region;

forming a first impurity region of a first conductive type at the transistor region of a first side of the gate electrode;

forming a first sidewall of a first insulating layer and a second sidewall of a second insulating layer at the first and a second side of the gate electrode;

forming a second impurity region of the first conductive type at the transistor region of the first side of the gate electrode;

applying a photoresist layer on the semiconductor substrate, and patterning the photoresist layer to cover the transistor region through an exposing and developing process;

forming a third impurity region of a second conductive type at the photodiode region using the patterned photoresist as a mask;

selectively removing a portion of the first sidewall between the second sidewall and the gate electrode at a predetermined thickness using the patterned photoresist layer as a mask;

covering the gate electrode by reflowing the patterned photoresist layer at a predetermined temperature;

selectively removing the second sidewall using the reflowed photoresist layer as a mask; and

forming a fourth impurity region of the first conductive type at the second side of the gate electrode.

2. The method according to claim 1 , wherein the second impurity region is formed deeper in the substrate than the first impurity region.

3. The method according to claim 1 , further comprising forming an oxide layer on the gate electrode at a thickness of 60 Å and less.

4. The method according to claim 1 , wherein the reflowing of the photoresist is performed at a temperature of 100° C. to 300° C.

5. The method according to claim 1 , further comprising performing a thermal process on the substrate after forming the fourth impurity region.

6. The method according to claim 1 , wherein the first insulating layer and the second insulating layer are formed of insulating layers having a different etching selectivity.

7. The method according to claim 1 , wherein the second sidewall is selectively removed by a wet etching process.

8. The method according to claim 1 , wherein the fourth impurity region is formed deeper into the substrate than the first impurity region.

9. The method according to claim 1 , wherein forming the third impurity region comprises implanting BF 2 or Boron.

10. The method according to claim 9 , wherein the BF 2 is implanted at dose of 1×10 11 to 5×10 12 atoms/cm 2 .

11. The method according to claim 9 , wherein implanting BF 2 is performed at an implanting energy of less than 40 KeV.

12. The method according to claim 9 , wherein the third impurity region has 1×10 16 to 5×10 17 atoms/cm 3 .

13. The method according to claim 1 , wherein the first insulating layer is an oxide layer, and the second insulating layer is a nitride layer.

14. The method according to claim 1 , wherein the first insulating layer is 150 Å to 250 Å, and the second insulating layer is 700 Å to 900 Å.

15. The method according to claim 1 , wherein forming a first sidewall of a first insulating layer and a second sidewall of a second insulating layer, comprises performing an etch-back process on the first insulating layer and the second insulating layer.

16. The method according to claim 1 , wherein selectively removing a portion of the first sidewall comprises performing a wet etching process on the first insulating layer using the patterned photoresist layer as a hard mask.

17. The method according to claim 1 , wherein covering the gate electrode reflows the patterned photoresist layer to be one-dimensionally extended about 0.4 μm and less.

18. The method according to claim 1 , wherein the reflowed patterned photoresist layer does not exceed covering the gate electrode.