Multiple circuit blocks with interblock control and power conservation
View Patent ↗A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.
1. A data processor built in a semiconductor chip, comprising:
a first means for including a central processing unit;
a second means for including a base band processing unit and an I/O unit inputting or outputting a plurality of signals to or from outside of said data processor;
a first voltage line coupled to said first means;
a second voltage line coupled to said second means; and
a control means,
wherein said data processor has a plurality of operation modes including an operation mode and a standby mode,
wherein said first means is supplied with a first operational level voltage from said first voltage line in said operation mode, is not supplied with said operational level voltage in said standby mode,
wherein said second means is supplied with a second operational level voltage in said operation mode and standby modes,
wherein said first means couples to said second means via a data signal line and a memory unit,
wherein said control means controls said memory unit to provide a signal from said first means to said second means in said operation mode,
wherein said control means controls said memory unit to store the signal from said first means before said operation mode is changed to said standby mode, and
wherein said base band processing unit is capable of outputting a signal to outside of said data processor via said I/O unit in said standby mode.
2. The data processor according to claim 1 ,
wherein said second means receives said signal stored in said memory unit in said standby mode.
3. The data processor according to claim 2 ,
wherein said CPU fetches an instruction from said memory unit, and executes said instruction in said operation mode.
4. The data processor according to claim 1 ,
wherein said memory unit is supplied with the second operational level voltage in said operation mode and said standby mode.