Semiconductor integrated circuit device with reduced leakage current
View Patent ↗The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A semiconductor integrated circuit device comprising:
a logic circuit including at least one N channel type MOS transistor and at least one P channel type MOS transistor, drains of each of said at least one N channel type transistor and each of said at least one P channel type MOS transistor being coupled to each other; and
a switch circuit for keeping a first source line to which a source electrode of each of the at least one P channel type MOS transistor is connected at a first potential in a first condition, and keeping said first source line at a second potential in a second condition,
wherein a source electrode of said at least one N channel type MOS transistor is coupled to a second source line to which a source electrode of each of the at least one N channel type MOS transistor is connected,
wherein said first source line is coupled to said switch circuit; and
wherein an insulating layer for use in a gate of either of said at least one N channel type MOS transistor or said at least one P channel type MOS transistor has a thickness of 4 nm or less.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein a substrate electrode of said at least one P channel type MOS transistor is set to said first potential.
3. The semiconductor integrated circuit device according to claim 1 ,
wherein a substrate electrode of said at least one N channel type MOS transistor is coupled to said second source line.
4. The semiconductor integrated circuit device according to claim 3 ,
wherein a substrate electrode of said at least one P channel type MOS transistor is set to said first potential.
5. The semiconductor integrated circuit device according to claim 1 ,
wherein a gate tunnel leakage current of either of said at least one N channel type MOS transistor or said at least one P channel type MOS transistor in an active mode is at least 10 −12 A/μm 2 .
6. The semiconductor integrated circuit device according to claim 5 ,
wherein a substrate electrode of said at least one P channel type MOS transistor is set to said first potential.
7. The semiconductor integrated circuit device according to claim 5 ,
wherein a substrate electrode of said at least one N channel type MOS transistor is coupled to said first source line.
8. The semiconductor integrated circuit device according to claim 7 ,
wherein a substrate electrode of said at least one P channel type MOS transistor is set to said first potential.
9. The semiconductor integrated circuit device according to claim 1 ,
wherein the first potential is higher than the second potential, and
wherein the logic circuit is in an operating state in the first condition and is in a standby state in the second condition.
10. A semiconductor integrated circuit device comprising:
a logic circuit including at least one N channel type MOS transistor and at least one P channel type MOS transistor, drains of said at least one N channel type transistor and said at least one P channel type MOS transistor being coupled to each other; and
a switch circuit for keeping a first source line to which a source electrode of the at least one P channel type MOS transistor is connected at a first potential in a first condition, and keeping said first source line at a second potential in a second condition,
wherein a source electrode of said at least one N channel type MOS transistor is coupled to a second source line to which a source electrode of the at least one N channel type MOS transistor is connected,
wherein said first source line is coupled to said switch circuit; and
wherein a gate tunnel leakage current of either of said N at least one channel type MOS transistor or said at least one P channel type MOS transistor in an active mode is at least 10 −12 A/μm 2 .
11. The semiconductor integrated circuit device according to claim 10 ,
wherein a substrate electrode of said at least one P channel type MOS transistor is set to said first potential.
12. The semiconductor integrated circuit device according to claim 10 ,
wherein a substrate electrode of said at least one N channel type MOS transistor is coupled to said second source line.
13. The semiconductor integrated circuit device according to claim 12 ,
wherein a substrate electrode of said at least one P channel type MOS transistor is set to said first potential.
14. The semiconductor integrated circuit device according to claim 10 ,
wherein the first potential is higher than the second potential, and
wherein the logic circuit is in an operating state in the first condition and is in a standby state in the second condition.