Resistance variable memory with temperature tolerant materials
View Patent ↗A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb 2 Se 3 , and a metal-chalcogenide layer and methods of forming such a memory device.
1. A method of forming a resistance variable memory device, comprising:
providing a substrate;
providing a first electrode over said substrate;
providing a second electrode over said substrate;
forming a Sb 2 Se 3 glass layer between said first electrode and said second electrode;
and forming a tin-selenide metal-chalcogenide layer between said Sb 2 Se 3 glass layer and said second electrode.
2. The method of claim 1 , further comprising providing an address line electrically connected with said first electrode.
3. The method of claim 2 , wherein said address line and said first electrode are the same layer.
4. The method of claim 1 , wherein said first electrode comprises tungsten.
5. The method of claim 1 , wherein said second electrode comprises tungsten.
6. The method of claim 1 , further comprising forming a metal layer between said metal-chalcogenide layer and said second electrode.
7. The method of claim 6 , further comprising forming a first chalcogenide glass layer between said metal-chalcogenide layer and said second electrode.
8. The method of claim 7 , further comprising forming a second chalcogenide glass layer between said metal layer and said second electrode.
9. The method of claim 8 , wherein at least one of said first chalcogenide glass layer and said second chalcogenide glass layer comprises germanium selenide.
10. The method of claim 9 , wherein said germanium selenide has a stoichiometry of about Ge 40 Se 60 .
11. The method of claim 6 , wherein said metal layer comprises at least one of antimony and silver.
12. The method of claim 1 , further comprising the act of forming a conducting channel within said Sb 2 Se 3 glass layer with a conditioning step.
13. The method of claim 12 , wherein said conditioning step comprises applying a voltage pulse across said Sb 2 Se 3 glass layer and said metal-chalcogenide layer.
14. The method of claim 12 , further comprising forming a conductive pathway at said conducting channel.