Process for producing silicon semiconductor wafers with defined defect properties, and silicon semiconductor wafers having these defect properties

1. A process for producing silicon semiconductor wafers, comprising:

pulling a silicon single crystal using the Czochralski method and processing to form semiconductor wafers, a ratio V/G of pulling rate V and axial temperature gradient G at a growth front during the pulling of the single crystal being controlled to produce agglomerated vacancy defects above a critical size in the single crystal, the agglomerated vacancy defects, in a region of the semiconductor wafer that is of relevance to electronic components, the agglomerated vacancy defects exhibiting shrinkage during production of the components, such that the size of the agglomerated vacancy defect in this region no longer exceeds the critical size, wherein the ratio V/G is controlled such that the following formula is satisfied for G at every radial position of the single crystal:

(V/G−ξc)≦α·D 2 ·G 2 , where α is a proportionality constant having the value 0.56·10 8 ±10% mm 2 min −1 K −3 , D is the critical size and ξc is the critical value at which no type of point defect is dominant.

2. The process of claim 1 , further comprising determining the critical size with the aid of a test wafer which is subjected to a treatment which simulates the production of the components in terms of the application of heat and generation of silicon interstitials.

3. The process of claim 2 , wherein an oxide layer with a thickness of from 1 to 2000 nm is produced on the test wafer.

4. The process of claim 2 , wherein phosphorus is made to diffuse into the test wafer.

5. The process of claim 1 , wherein the ratio V/G is controlled in such a manner that the following relationship applies:

V/G=ξc.

6. The process of claim 1 , wherein the ratio V/G is controlled in such a manner that no Lpit's are formed.

7. A method for producing silicon semiconductor wafers, comprising pulling a silicon single crystal by the Czochralski method, said pulling process predetermining an axial temperature gradient G at a growth front; determining a critical size D of shrinkable agglomerated vacancy defects by subjecting a test wafer having agglomerated vacancy defects to at least one heat treatment which simulates a heat treatment during an electronic device forming process injecting silicon interstitials into the wafer;

pulling a silicon single crystal with said pulling process; and

controlling a ratio V/G of pulling rate V and said axial temperature gradient G during the pulling of the single crystal so that the following formula is satisfied for G at every radial position of the single crystal: (V/G−ξc)≦α·D 2 ·G 2 , where α is a proportionality constant having the value 0.56·10 6 ±10% mm 2 min −1 K −3 and ξc is the critical value at which no type of point defect is dominant; producing wafers from the silicon single crystal.

8. The process of claim 7 , wherein an oxide layer with a thickness of from 1 to 2000 nm is produced on the test wafer.

9. The process of claim 7 , wherein phosphorus is made to diffuse into the test wafer.

10. The process of claim 7 , wherein the ratio V/G is controlled in such a manner that the following relationship applies: V/G≧ξ c .

11. The process of claim 7 , wherein the ratio V/G is controlled in such a manner that no Lpit's are formed.

12. The process of claim 7 , further comprising fabricating electronic devices on the silicon wafer by performing an electronic device fabrication process to produce said electronic devices on said wafer, agglomerated vacancy defects shrinking during said device fabrication process to a size which does not affect device performance.

13. The process of claim 12 , wherein prior to device fabrication, the wafer has agglomerated vacancy defects of a size which will affect device performance.