IP Library Granted Patent US 7,537,992
Granted Patent B2
US 7,537,992 · App. 11/454,350 · Granted May 26, 2009

Method for manufacturing flash memory device

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Quick Facts
Patent No.
US 7,537,992
App. No.
11/454,350
Granted
May 26, 2009
Kind
B2
Abstract

A flash memory device incorporating: a semiconductor substrate having an active region and a field region defined therein; a device isolation layer formed in the field region of the substrate; a floating gate having an edge portion overlapping the device isolation layer, the overlapped portion being etched back a depth about equal to a height of a protruding portion of the device isolation layer, the floating gate having a tunneling oxide layer interposed in the active region of the semiconductor substrate; and a gate insulation layer and a control gate sequentially formed on the floating gate.

Claims (33)

1. A method of manufacturing a flash memory device, comprising:

preparing a semiconductor substrate having an active region and a field region;

forming a device insulating layer in the field region;

forming a tunneling oxide layer on the active region;

forming a first polysilicon layer on the tunneling oxide layer;

coating a photoresist on the first polysilicon layer and selectively patterning the coated photoresist to define a floating gate region, wherein the patterned photoresist is only on the active region;

etching by a predetermined thickness a portion of the first polysilicon layer overlapping the device insulating layer using the patterned photoresist as a mask;

forming a polymer on sides of the patterned photoresist;

forming a floating gate by selectively removing the polysilicon layer using the photoresist and the polymer as a mask; and

removing the photoresist and the polymer.

2. The method according to claim 1 , further comprising:

forming a gate insulating layer on the floating gate; and

forming a control gate on the gate insulating layer.

3. The method according to claim 1 , wherein the polymer is formed using a fluorine-based gas.

4. The method according to claim 1 , wherein removing the photoresist and the polymer comprises performing an oxygen ashing process and a cleaning process.

5. The method according to claim 1 , further comprising forming a planarization layer on the first polysilicon layer prior to the coating of the photoresist.

6. The method according to claim 5 , wherein the planarization layer is an anti-reflective layer formed of an organic material.

7. The method according to claim 1 , wherein etching an overlapped portion of the first polysilicon layer causes the first polysilicon layer to have the same roughness as a surface of the first polysilicon layer formed on the active region.

8. A method of manufacturing a flash memory device, comprising:

providing a substrate having a field region and an active region;

forming a device isolation layer in the field region;

forming a polysilicon layer on the substrate;

forming a planarization layer on the polysilicon layer;

coating a photoresist on the planarization layer, and patterning the coated photoresist, wherein the patterned photoresist is only on the active region;

removing a portion of the planarization layer and the polysilicon layer formed on the field region by using the patterned photoresist as a mask, such that a surface of the polysilicon layer formed on the field region has the same roughness as a surface of the polysilicon layer below the patterned photoresist;

forming a polymer sidewall on the patterned photoresist; and

etching the polysilicon layer to form a floating gate.

9. The method according to claim 8 , wherein the floating gate is formed by etching the polysilicon layer formed on the field region using the polymer sidewall and patterned photoresist as a mask.

10. The method according to claim 8 , further comprising forming a tunneling oxide layer on the active region of the substrate.

11. The method according to claim 8 , wherein both edges of the floating gate overlap a portion of the device isolation layer formed in the field region.

12. The method according to claim 8 , wherein the planarization layer is formed of an organic material.

13. The method according to claim 8 , wherein the polymer is formed using a fluorine-based gas.

14. The method according to claim 8 , further comprising removing the photoresist and the polymer by using an oxygen ashing process and a cleaning process.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041374/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017989 FRAME 0614. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ENTIRE INTEREST. Recorded Nov 18, 2008
From: KWAK, SUNG HO
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 021853/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2006
From: HO, KWAK SUNG
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017989/0614 →