Site-specific nanoparticle self-assembly
Disclosed herein are methods of self-assembling nanoparticles on specific sites of a substrate. The method generally includes introducing a p-type dopant species to at least a portion of an n-type substrate or introducing an n-type dopant species to at least a portion of a p-type substrate, wherein the dopant species creates a surface charge opposite in polarity to that of the substrate surface prior to the introducing; contacting the nanoparticles with the surface of the substrate; and self-assembling a layer of the nanoparticles on p-type regions of the substrate. The methods described herein may be used in the formation of sub-22 nanometer channels, which find use in field-effect transistors, electronic chips, nanoscale biosensors, photonic band gap devices, lasers in optoelectronics and photonics chips, as well as nano-electro-mechanical devices (NEMS).
1. A method for site-specific self-assembly of nanoparticles on a surface of a substrate, the method comprising:
introducing p-type dopant species to at least a portion of an n-type substrate or introducing n-type dopant species to at least a portion of a p-type substrate, wherein the dopant species creates a surface charge opposite in polarity to that of the substrate surface prior to the introducing;
contacting the nanoparticles with the surface of the substrate; and
self-assembling a layer of the nanoparticles on p-type regions of the substrate.
2. The method of claim 1 , further comprising redistributing the dopant species to modify the size and/or shape of a doped region on the substrate.
3. The method of claim 2 , wherein the redistributing of dopant species comprises rapid thermal annealing, ion implantation, ion implantation and rapid thermal annealing, electron beam annealing, plasma hot gas annealing, laser annealing, or a combination comprising at least one of the foregoing.
4. The method of claim 1 , further comprising depositing a mask layer on the surface of the substrate prior to introducing the dopant species.
5. The method of claim 4 , wherein the mask layer comprises a thermally grown oxide, silicon nitride, a semiconductor that can be selectively etched and patterned, or a combination comprising at least one of the foregoing.
6. The method of claim 5 , wherein the semiconductor that can be selectively etched and patterned comprises Si, Ge, GaAs, ZnS, CdSe, ZnSe, ZnSSe, InGaAs, GaN, InP, or a combination comprising at least one of the foregoing.
7. The method of claim 4 , further comprising removing at least a portion of the mask layer prior to introducing the dopant species.
8. The method of claim 4 , further comprising removing the mask layer in its entirety prior to contacting the nanoparticles with the surface of the substrate.
9. The method of claim 1 , further comprising depositing a layer of an insulating material or a semiconducting material on a p-type region of the substrate prior to contacting the nanoparticles with the surface of the substrate, wherein the layer of the nanoparticles self-assembles on the layer of the insulating material or the semiconducting material.
10. The method of claim 9 , wherein the layer of the insulating material or the semiconducting material has a thickness of about 1 nanometer to about 15 nanometers.
11. The method of claim 9 , wherein the insulating material comprises SiO 2 , HfO 2 , HfAlO 2 , PZT, ZrO 2 , BaSrTiO 3 , BaTiO 3 , ZnO, ZnMgO, Al 2 O 3 , or a combination comprising at least one of the foregoing insulators.
12. The method of claim 9 , wherein the semiconducting material comprises ZnS, GaAs, AlGaN, ZnBeS, ZnBeSSe, ZnBeSe, AlGaInP, or a combination comprising at least one of the foregoing semiconductors.
13. The method of claim 1 , wherein the nanoparticles comprise a silicon oxide-coated-silicon, silicon oxide, silane, tetraethoxysilane, or a combination comprising at least one of the foregoing.
14. The method of claim 1 , wherein the surface of the substrate comprises a metal, a semiconductor, an insulator, a dielectric, or a combination comprising at least one of the foregoing.
15. The method of claim 1 , further comprising consolidating the self-assembled layer of nanoparticles into a thin film by heating the nanoparticles.
16. The method of claim 1 , further comprising using the self-assembled layer of nanoparticles to form a field effect transistor.
17. The method of claim 16 , further wherein the field effect transistor is a sub-22 nanometer gate field effect transistor.
18. A method of forming a p-channel field effect transistor, comprising:
depositing a patterned mask layer on a surface of an n-type substrate;
introducing p-type dopant species to at least a portion of the unmasked surface of the n-type substrate to form p-type regions on the surface of the n-type substrate;
removing the patterned mask layer from the surface of the n-type substrate;
contacting a plurality of nanoparticles with the surface of the n-type substrate;
self-assembling a layer of the nanoparticles on the p-type regions of the surface of the n-type substrate;
consolidating the layer of the nanoparticles into a thin film by heating the nanoparticles;
depositing a gate insulator on the thin film;
depositing a gate material on the gate insulator;
etching the gate material and the gate insulator from a source location and from a drain location;
depositing a source material in the source location and a drain material in the drain location; and
depositing contacts for the source, gate, and drain.
19. The method of claim 18 , wherein the n-type substrate comprises Si, Ge, SiGe, GaAs, InGaAs, ZnS, ZnSe, SiC, or GaN.
20. The method of claim 18 , further comprising redistributing the p-type dopant species to modify the size and/or shape of the doped region on the surface of the n-type substrate.
21. The method of claim 18 , wherein the gate of the p-channel field effect transistor is a sub-22 nanometer gate.
22. The method of claim 18 , wherein the nanoparticles comprise silicon oxide-coated-silicon, silicon oxide, a silane, tetraethoxysilane, or a combination comprising at least one of the foregoing.
23. A p-channel field effect transistor made by the process of claim 18 .
24. A method of forming an n-channel field effect transistor, comprising:
depositing a patterned mask layer on a surface of a p-type substrate;
introducing n-type dopant species to at least a portion of the unmasked surface of the p-type substrate to form n-type regions on the surface of the p-type substrate;
removing the patterned mask layer from the surface of the p-type substrate;
contacting a plurality of nanoparticles with the surface of the p-type substrate;
self-assembling a layer of the nanoparticles on the p-type regions of the surface of the p-type substrate;
depositing a layer of a dielectric material on the surface of the p-type substrate, wherein the nanoparticles serve as a mask for the deposition of the layer of the dielectric material;
removing the nanoparticle mask from the surface of the p-type substrate;
depositing a gate insulator on the surface of the p-type substrate;
depositing a gate material on the gate insulator;
etching the gate material and the gate insulator from a source location and from a drain location;
depositing a source material in the source location and a drain material in the drain location; and
depositing contacts for the source, gate, and drain.
25. The method of claim 24 , wherein the p-type substrate comprises Si, Ge, SiGe, GaAs, InGaAs, ZnS, ZnSe, SiC, or GaN.
26. The method of claim 24 , further comprising redistributing the n-type dopant species to modify the size and/or shape of the doped region on the surface of the p-type substrate.
27. The method of claim 24 , wherein the gate of the n-channel field effect transistor is a sub-22 nanometer gate.
28. The method of claim 24 , wherein the nanoparticles comprise silicon oxide-coated-silicon, silicon oxide, a silane, tetraethoxysilane, or a combination comprising at least one of the foregoing.
29. An n-channel field effect transistor made by the process of claim 24 .
30. A complementary field effect transistor comprising the p-channel field effect transistor of claim 23 and the n-channel field effect transistor of claim 29 .