Programmable resistive RAM and manufacturing method
Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.
1. An integrated circuit with nonvolatile memory cells, comprising:
circuitry accessing particular nonvolatile memory cells, the circuitry including: 1) conductive rows accessing the nonvolatile memory cells by row and 2) conductive columns accessing the nonvolatile memory cells by column; and
programmable resistive elements of the nonvolatile memory cells, each of the programmable resistive elements conductively connected with the conductive rows and the conductive columns, wherein the programmable resistive elements are positioned vertically above the conductive rows and the conductive columns.
2. The circuit of claim 1 , wherein the programmable resistive elements includes at least one of: a chalcogenide, Pr x Ca y MnO 3 , PrSrMnO 3 , ZrO x , TCNQ, and PCBM.
3. The circuit of claim 1 , wherein said circuitry includes:
a first dielectric layer covering the conductive rows, wherein the conductive columns are above the first dielectric layer;
a second dielectric layer at least partly adjacent to the conductive columns and at least partly adjacent to the first dielectric layer;
a third dielectric layer at least partly covering the second dielectric layer; and
interlayer contacts adjacent to the conductive columns, including:
conductive lining conductively connecting the conductive columns and the programmable resistive elements;
dielectric lining allowing conductive connection between the conductive rows and the conductive lining only via the programmable resistive elements; and
conductive structures conductively connecting the conductive rows and the programmable resistive elements.
4. The circuit of claim 3 , wherein the first dielectric layer includes at least one of: SiO x and material having a dielectric constant lower than 3;
the second dielectric layer includes at least one of: SiN x , SiO x N y , and SiO x ;
the third dielectric layer includes at least one of: SiOx, material having a dielectric constant lower than 3 , SiO x N y , and SiN x ;
the conductive lining includes at least one of: TiN, Ti, TiN/Ti bilayer, TaN, W, Al, LiNbO 3 , IrO x , RuOx, YBaCuO, LaCaMnO 3 , Pt, metal-silicide, doped poly-Si; and
the dielectric lining includes at least one of: SiO x , SiO x N y , SiN x , SrTiO 3 .
5. The circuit of claim 3 , wherein said circuitry further comprises:
a fourth dielectric layer at least partly between the programmable resistive elements and the conductive columns.
6. The circuit of claim 5 , wherein said fourth dielectric layer includes at least one of: SiOx, SiOxNy, SiNx, SrTiO 3 , and AlOx.
7. The circuit of claim 1 , wherein said conductive columns include:
a first layer of conductive columns; and
a second layer of conductive columns at least partly covering the first layer of conductive columns,
wherein a stairstep profile characterizes said first layer of conductive columns and said second layer of conductive columns.
8. The circuit of claim 7 , wherein said first layer of conductive columns includes at least one of: TiN, Ti, TiN/Ti bilayer, W/TiN bilayer, AlCu/TiN bilayer, doped poly-Si, and metal-silicide; and
said second layer of conductive columns includes at least one of: AlCu, TiN/AlCu bilayer, TiN/Ti/AlCu trilayer, W, metal-silicide, and doped poly-Si.