Phase locked loop fast lock method
The present invention is a method to rapidly lock a type II phase locked loop (PLL) after a frequency jump without degrading the output signal much. The method to decrease the settling time and improve the quality of the output clock during the settling disclosed herein comprises of the following broad steps: Estimate new frequency offset with a separate circuit outside the PLL loop to measure the frequency of the input signal accurately. Ramp integrator to the new frequency offset. Do phase build out or phase pull-in. The remaining phase offset is build out when no edge to edge alignment is required. Otherwise, the remaining phase offset is pulled in while the integrator in the PLL's loop filter is disabled. Reduce the PLL bandwidth and/or lower damping to let the PLL settle. Switch the PLL to final bandwidth and damping required by the application.
1. A method of locking a phase lock loop (PLL) after a lock lost is detected, comprising:
estimating a new frequency offset using a circuit separate from the PLL;
integrator ramping to the new frequency offset;
adjusting the phase of the PLL based on the new frequency offset; and
decaying the PLL to settle to the frequency jump.
2. The method of claim 1 , wherein the step of estimating comprises using a separate PLL system that outputs the new frequency offset to the PLL.
3. The method of claim 1 , wherein the step of estimating comprises using a local clock cycle counter counts the number of local clock cycles during a predetermined number of reference clock cycles.
4. The method of claim 1 , wherein the step of adjusting comprises performing phase build out if a zero phase offset is not required, or performing a phase pull in if a zero phase is required.
5. The method of claim 4 , wherein the step of performing a phase build out comprises:
resetting a phase detector of the PLL;
measuring a value of the shortest phase offset between an input of a reference clock and a PLL feedback clock;
storing the value in a register; and
subtracting the value from a phase value from the phase detector.
6. The method of claim 4 , wherein the step of performing a phase pull in comprises disabling the integrator such that the integrator does not see a phase value from a phase detector of the PLL.
7. The method of claim 1 , wherein the step of decaying comprises relaxing the bandwidth and/or damping of the PLL.
8. A method of locking a phase lock loop (PLL) after a lock lost is detected, comprising:
estimating a new frequency offset using a circuit separate from the PLL;
integrator ramping to the new frequency offset;
adjusting the phase of the PLL based on the new frequency offset by performing phase build out if a zero phase offset is not required, or performing a phase pull in if a zero phase is required; and
decaying the PLL to settle to the frequency jump by relaxing the bandwidth and/or damping of the PLL.
9. The method of claim 8 , wherein the step of estimating comprises using a separate PLL system that outputs the new frequency offset to the PLL.
10. The method of claim 8 , wherein the step of estimating comprises using a local clock cycle counter counts the number of local clock cycles during a predetermined number of reference clock cycles.
11. The method of claim 8 , wherein the step of performing a phase build out comprises:
resetting a phase detector of the PLL;
measuring a value of the shortest phase offset between an input of a reference clock and a PLL feedback clock;
storing the value in a register; and
subtracting the value from a phase value from the phase detector.
12. The method of claim 8 , wherein the step of performing a phase pull in comprises disabling the integrator such that the integrator does not see a phase value from a phase detector of the PLL.
13. A phase lock loop (PLL) capable of fast locking after a lock lost is detected, comprising:
a lock detector for detecting a lock lost of the PLL;
an input for receiving an estimated new frequency offset from using a circuit separate from the PLL after lock lost;
an integrator for ramping to the new frequency offset; and
a phase adjuster for adjusting the phase of the PLL based on the new frequency offset by performing phase build out if a zero phase offset is not required, or performing a phase pull in if a zero phase is required and decaying the PLL to settle to the frequencyjump by relaxing the bandwidth and/or damping of the PLL.
14. The PLL of claim 13 , wherein the frequency estimator comprises a separate PLL system that outputs the new frequency offset to the PLL.
15. The PLL of claim 13 , wherein the frequency estimator comprises a local clock cycle counter that counts the number of local clock cycles during a predetermined number of reference clock cycles.
16. The PLL of claim 13 , wherein the phase build is performed using a register to store a value representing a value of the shortest phase offset between an input of a reference clock and a PLL feedback clock and the value from a phase value from the phase detector, after a phase detector of the PLL has been reset.