Metal pad or metal bump over pad exposed by passivation layer
View Patent ↗A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.
1. A semiconductor chip comprising:
a semiconductor substrate;
a transistor on said semiconductor substrate;
a copper pad over said semiconductor substrate;
a tantalum-containing layer at a sidewall and a bottom surface of said copper pad;
a copper seed layer at said sidewall and said bottom surface, wherein said copper seed layer is between said tantalum-containing layer and said copper pad;
a single layer of a titanium-containing material directly on a top surface of said copper pad;
a gold seed layer on said single layer of said titanium-containing material, wherein said gold seed layer contacts said single layer of said titanium-containing material; and
an electroplated gold layer on said gold seed layer, wherein said electroplated gold layer has a thickness between 0.1 and 30 micrometers.
2. The semiconductor chip of claim 1 further comprising a passivation layer over said semiconductor substrate, wherein an opening in said passivation layer is over a contact point of said top surface of said copper pad, and said contact point is at a bottom of said opening, wherein said single layer of said titanium-containing material is directly on said contact point, wherein said passivation layer comprises a nitride layer.
3. The semiconductor chip of claim 1 further comprising an insulating layer over said semiconductor substrate, wherein said copper pad is further over said insulating layer, wherein said insulating layer has a dielectric constant less than 3.
4. The semiconductor chip of claim 3 , wherein said insulating layer comprises a compound comprising silicon, oxygen, nitrogen and carbon.
5. The semiconductor chip of claim 1 , wherein said electroplated gold layer is configured to be wirebonded thereto.
6. The semiconductor chip of claim 1 , wherein the semiconductor chip is configured for a tape-automated bonding (TAB) package.
7. The semiconductor chip of claim 1 , wherein the semiconductor chip is configured for a chip-on-film (COF) package.
8. The semiconductor chip of claim 1 , wherein the semiconductor chip is configured for a chip-on-glass (COG) package.
9. The semiconductor chip of claim 1 , wherein said single layer of said titanium-containing material comprises a titanium-tungsten alloy.
10. A semiconductor chip comprising:
a semiconductor substrate;
a transistor on said semiconductor substrate;
a copper pad over said semiconductor substrate;
a metal layer on a sidewall and a bottom surface of said copper pad;
a passivation layer over said semiconductor substrate, wherein an opening in said passivation layer is over a contact point of said copper pad, and said contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride layer;
a single layer of a titanium-containing material directly on said contact point and directly on a top surface of said passivation layer;
a gold seed layer on said single layer of said titanium-containing material, wherein said gold seed layer contacts said single layer of said titanium-containing material; and
an electroplated gold layer on said gold seed layer, wherein said electroplated gold layer has a thickness between 0.1 and 30 micrometers.
11. The semiconductor chip of claim 10 further comprising an insulating layer over said semiconductor substrate, wherein said copper pad is further over said insulating layer, wherein said insulating layer has a dielectric constant less than 3.
12. The semiconductor chip of claim 11 , wherein said insulating layer comprises a compound comprising silicon, oxygen, nitrogen and carbon.
13. The semiconductor chip of claim 10 , wherein said electroplated gold layer is configured to be wirebonded thereto.
14. The semiconductor chip of claim 10 , wherein said semiconductor chip is configured for a tape-automated bonding (TAB) package.
15. The semiconductor chip of claim 10 , wherein said semiconductor chip is configured for a chip-on-film (COF) package.
16. The semiconductor chip of claim 10 , wherein said semiconductor chip is configured for a chip-on-glass (COG) package.
17. The semiconductor chip of claim 10 , wherein said single layer of said titanium-containing material comprises a titanium-tungsten alloy.
18. The semiconductor chip of claim 10 , wherein said metal layer comprises tantalum.
19. A semiconductor chip comprising:
a semiconductor substrate;
a transistor on said semiconductor substrate;
a copper pad over said semiconductor substrate;
a metal layer on a sidewall and a bottom surface of said copper pad;
a passivation layer over said semiconductor subtrate, wherein an opening in said passivation layer is over a contact point of said copper pad, and said contact point is at a bottom of said opening;
a single layer of a titanium-containing material directly on said contact point; and
a gold layer over said single layer of said titanium-containing material, wherein said semiconductor chip is configured for a chip-on-glass (COG) package.
20. The semiconductor chip of claim 19 , wherein said metal layer comprises tantalum.
21. The semiconductor chip of claim 19 , wherein said gold layer has a thickness between 0.1 and 30 micrometers.
22. The semiconductor chip of claim 19 , wherein said passivation layer comprises an insulating layer.
23. The semiconductor chip of claim 22 , wherein said insulating layer comprises silicon nitride.
24. The semiconductor chip of claim 22 , wherein said insulating layer comprises silicon oxynitride.
25. The semiconductor chip of claim 22 , wherein said insulating layer comprises silicon oxide.
26. A circuit component comprising:
a first dielectric layer;
a first copper layer over said first dielectric layer;
a barrier layer at a bottom of said first copper layer and at a sidewall of said first copper layer;
an aluminum-containing layer over a top surface of said first copper layer, wherein said aluminum-containing layer is connected to said first copper layer;
a passivation layer over said aluminum-containing layer, said first copper layer and said first dielectric layer, wherein said passivation layer contacts a sidewall of said aluminum-containing layer, wherein a first opening in said passivation layer is over a contact point of said aluminum-containing layer; and
a metal bump on said contact point, wherein said metal bump is connected to said contact point through said first opening, wherein said metal bump is connected to said first copper layer through said aluminum-containing layer, wherein said metal bump comprises a metal layer on said contact point and a gold layer on said metal layer, wherein said gold layer is configured for chip-on-glass (COG) bonding.
27. The circuit component of claim 26 , wherein said barrier layer comprises tantalum.
28. The circuit component of claim 26 , wherein said barrier layer comprises titanium.
29. The circuit component of claim 26 further comprising a second dielectric layer over said first dielectric layer, wherein said first copper layer is further in a second opening in said second dielectric layer, wherein said barrier layer has a portion between said sidewall of said first copper layer and a sidewall of said second opening.
30. The circuit component of claim 26 , wherein said passivation layer comprises a nitride layer.
31. The circuit component of claim 30 , wherein said nitride layer comprises silicon nitride.
32. The circuit component of claim 30 , wherein said nitride layer comprises silicon oxynitride.
33. The circuit component of claim 30 , wherein said passivation layer further comprises a silicon-oxide layer.
34. The circuit component of claim 26 , wherein said gold layer has a thickness between 2 and 30 micrometers.
35. The circuit component of claim 26 , wherein said metal layer comprises titanium.
36. The circuit component of claim 26 , wherein said metal layer comprises a second copper layer between said contact point and said gold layer.
37. The circuit component of claim 36 , wherein said metal layer further comprises a nickel layer between said second copper layer and said gold layer.
38. The circuit component of claim 36 , wherein said second copper layer has a thickness between 0.1 and 10 micrometers.
39. The circuit component of claim 36 , wherein said metal layer further comprises a titanium-containing layer between said contact point and said second copper layer.
40. The circuit component of claim 26 , wherein said metal layer is under said gold layer, but is not at a sidewall of said gold layer.