SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION
A system and method are provided for use in the context of a plurality of memory circuits. In use, first information is received in association with a first operation to be performed on at least one of the memory circuits. At least a portion of the first information is stored. Still yet, second information is received in association with a second operation to be performed on at least one of the plurality of memory circuits. To this end, the second operation may be performed utilizing the stored portion of the first information in addition to the second information.
1 . A method, comprising:
receiving first information in association with a first operation to be performed on at least one of a plurality of memory circuits;
storing at least a portion of the first information;
receiving second information in association with a second operation to be performed on at least one of the plurality of memory circuits; and
performing the second operation utilizing the stored portion of the first information in addition to the second information.
2 . The method of claim 1 , wherein the first operation includes a row operation.
3 . The method of claim 1 , wherein the second operation includes a column operation.
4 . The method of claim 1 , wherein the first information and second information include address information.
5 . The method of claim 4 , wherein the first information includes a first address bit set.
6 . The method of claim 5 , wherein the second information includes a second address bit set.
7 . The method of claim 5 , wherein the portion of the first address bit set includes at least one address bit.
8 . The method of claim 7 , wherein the at least one address bit is stored utilizing a bank index.
9 . The method of claim 8 , wherein the at least one address bit is retrieved utilizing the bank index during the second operation.
10 . The method of claim 8 , wherein the at least one address bit is utilized to generate a memory address during the second operation.
11 . The method of claim 1 , wherein a lookup table is utilized to perform the storing.
12 . The method of claim 1 , wherein the portion of the first information is stored for at least one clock cycle.
13 . The method of claim 1 , wherein the storing is carried out utilizing an interface circuit for interfacing the plurality of memory circuits and a system including a memory controller.
14 . The method of claim 13 , wherein the interface circuit is positioned on a dual in-line memory module (DIMM).
15 . The method of claim 13 , wherein the memory circuits each include dynamic random access memory (DRAM).
16 . The method of claim 15 , wherein the memory circuits each include a monolithic DRAM.
17 . The method of claim 16 , wherein the memory circuits are stacked.
18 . The method of claim 16 , wherein the memory circuits and the interface circuit are stacked.
19 . A method, comprising:
receiving a first set of address bits in association with a row operation;
storing at least a portion of the first set of address bits;
receiving a second set of address bits in association with a column operation; and
performing the column operation utilizing the stored portion of the first set of address bits in addition to the second set of address bits.
20 . A sub-system, comprising:
a circuit in communication with a plurality of memory circuits and a system, the circuit operable to store at least a portion of information received in association with a first operation for use in performing a second operation.