Patent Assignment
Reel/Frame 023525/0835
Assignment of Assignor's Interest
Recorded: 2009-11-18
Pages: 10
Assignor
METARAM, INC.
Executed: 2009-09-11
Assignee
GOOGLE INC.
1600 AMPHITHEATRE PARKWAY, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(71)
Method and apparatus for integrating multi-chip memory devices
Application:
60/693,631 →
Methods and apparatus of stacking DRAMS
Application:
60/713,815 →
Multi-rank memory buffer and memory stack
Application:
60/772,414 →
Memory systems and memory modules
Application:
60/814,234 →
Stackable Low-Profile Lead Frame Package
Patent:
8,796,830 →
Application:
11/515,167 →
Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
Application:
11/474,076 →
Publication:
US US20070014168A1
Simulating a Different Number of Memory Circuit Devices
System and Method for Simulating an Aspect of a Memory Circuit
System and Method for Delaying a Signal Communicated from a System to at Least One of a Plurality of Memory Circuits
System and Method for Storing at Least a Portion of Information Received in Association with a First Operation for Use in Performing a Second Operation
Application:
11/461,435 →
Publication:
US US20080025136A1
A Memory Refresh Apparatus and Method
Multiple-Component Memory Interface System and Method
Application:
11/461,441 →
Publication:
US US20080028135A1
Method and Apparatus for Refresh Management of Memory Modules
Application:
11/828,181 →
Publication:
US US20080028136A1
Methods and Apparatus of Stacking Drams
Memory Circuit Simulation System and Method with Power Saving Capabilities
Combined Signal Delay and Power Saving for Use with a Plurality of Memory Circuits
Memory Circuit Simulation System and Method with Refresh Capabilities
Autonomous Refresh and Data Protection in Memory Circuits
Application:
60/823,229 →
Apparatus and Method for Power Management of Memory Circuits by a System or Component Thereof
Application:
11/538,041 →
Publication:
US US20080082763A1
System and method for increasing capacity and performance of flash storage
Application:
60/849,631 →
System and Method for Increasing Capacity, Performance, and Flexibility of Flash Storage
Memory Subsystem and Method
Application:
60/865,624 →
Multi-Rank Partial Width Memory Modules
Application:
60/865,623 →
System and Method for Memory Control
Application:
60/865,627 →
Adjusting the Timing of Signals Associated with a Memory System
Memory Device with Emulated Characteristics
Memory Module with Memory Stack and Interface with Enhanced Capabilities
Memory module with memory stack
Application:
11/702,960 →
Publication:
US US20080126690A1
System and Method for Reducing Command Scheduling Constraints of Memory Circuits
Translating an Address Associated with a Command Communicated Between a System and Memory Circuits
Memory Systems and Memory Modules
Method and Apparatus For Refresh Management of Memory Modules
Application:
11/828,182 →
Publication:
US US20080028137A1
Stacked Dimm Memory Interface
Patent:
8,386,722 →
Application:
12/144,396 →
System and Method for Simulating an Aspect of a Memory Circuit
Emulation Of Abstracted DIMMS Using Abstracted DRAMS
Application:
61/030,534 →
Providing Additional Space Between an Integrated Circuit and a Circuit Board for Positioning a Component Therebetween
Patent:
8,080,874 →
Application:
11/855,826 →
Multi-Rank Partial Width Memory Modules
Patent:
8,130,560 →
Application:
11/939,432 →
Optimal Channel Design for Memory Devices for Providing a High-Speed Memory Interface
Patent:
8,111,566 →
Application:
11/941,589 →
System and Method for Reducing Command Scheduling Constraints of Memory Circuits
Reducing Command Scheduling Constraints of Memory Circuits
Application:
11/929,261 →
Publication:
US US20080109595A1
Memory Device with Emulated Characteristics
Application:
11/929,286 →
Publication:
US US20080109206A1
Memory Apparatus Operable to Perform a Power-Saving Operation
Memory Device with Emulated Characteristics
Application:
11/929,403 →
Publication:
US US20080126687A1
Memory Apparatus Operable to Perform a Refresh Operation
Application:
11/929,417 →
Publication:
US US20080126688A1
Memory Device with Emulated Characteristics
Application:
11/929,432 →
Publication:
US US20080126689A1
Memory Device with Emulated Characteristics
Application:
11/929,450 →
Publication:
US US20080103753A1
A Method of Presenting a Memory Device Having an Emulated Memory Standard
Application:
11/929,483 →
Publication:
US US20080104314A1
Apparatus for Simulating an Aspect of a Memory Circuit
Memory Circuit System and Method
Memory Circuit System and Method
Refresh Management of Memory Modules
Method and apparatus for refresh management of memory modules
Application:
11/929,655 →
Publication:
US US20080109598A1
Embossed Heat Spreader
Application:
61/014,740 →
Interface Circuit System and Method for Performing Power Management Operations in Conjunction with Only a Portion of a Memory Circuit
Interface Circuit System and Method for Autonomously Performing Power Management Operations in Conjunction with a Plurality of Memory Circuits
Hybrid Memory Module
Patent:
8,397,013 →
Application:
12/057,306 →
Emulation of Abstracted Dimms Using Abstracted Drams
Methods and Apparatus of Stacking Drams
Embossed Heat Spreader
Patent:
8,081,474 →
Application:
12/203,100 →
Memory Subsystem With Ganged Ranks
Application:
61/083,878 →
Configurable Memory System with Interface Circuit
Patent:
8,335,894 →
Application:
12/508,496 →
Programming of Dimm Termination Resistance Values
Application:
61/185,585 →
Simulating a Memory Circuit
Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies
16
Power Saving System and Method for Use with a Plurality of Memory Circuits
Methods and Apparatus of Stacking Drams
System and Method for Power Management in Memory Systems
Interface Circuit System and Method for Performing Power Saving Operations During a Command-Related Latency
Interface Circuit System and Method for Performing Power Management Operations in Conjunction with Only a Portion of a Memory Circuit
Interface Circuit System and Method for Autonomously Performing Power Management Operations in Conjunction with a Plurality of Memory Circuits
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 1, 2006
From: FJELSTAD, JOSEPH C.
To: METARAM, INC.
Reel/Frame 018272/0219 →
Change of Name
Oct 2, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044101/0299 →
Change of Name
Oct 2, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044101/0405 →
Change of Name
Oct 2, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044101/0610 →
Change of Name
Oct 2, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044334/0466 →
Change of Name
Oct 2, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044277/0001 →
Change of Name
Oct 6, 2017
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 044142/0357 →