Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
View Patent ↗A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits
1. A sub-system, comprising:
an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to perform a power management operation in association with only a portion of the memory circuits;
wherein the interface circuit is operable to simulate at least one virtual memory circuit.
2. The sub-system of claim 1 , wherein the power management operation includes a power saving operation.
3. The sub-system of claim 2 , wherein the power saving operation includes a power down operation.
4. The sub-system of claim 1 , wherein the power management operation is initiated by at least one power management signal.
5. The sub-system of claim 4 , wherein the at least one power management signal includes at least one of a clock enable signal, and a chip select signal.
6. The sub-system of claim 1 , wherein the power management operation is initiated by at least one non-power management signal.
7. The sub-system of claim 1 , wherein the power management operation is initiated based on a state of one or more of the memory circuits.
8. The sub-system of claim 7 , wherein the state is selected from the group consisting of a status of the one or more of the memory circuits, a predetermined combination of commands issued to the one or more of the memory circuits, a predetermined pattern of commands issued to the one or more of the memory circuits, and a predetermined absence of commands issued to the one or more of the memory circuits.
9. The sub-system of claim 1 , wherein the power management operation is performed in association with only a portion of the at least one virtual memory circuit.
10. The sub-system of claim 1 , wherein the at least one virtual memory circuit includes a single virtual memory circuit.
11. The sub-system of claim 1 , wherein the power management operation includes powering down a first portion of the memory circuits while a second portion of the memory circuits is subject to at least one command.
12. The sub-system of claim 1 , wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).
13. The sub-system of claim 1 , wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).
14. The sub-system of claim 1 , wherein the interface circuit and the memory circuits take the form of a stack.
15. The sub-system of claim 14 , wherein the stack includes a single interface circuit.
16. The sub-system of claim 1 , wherein the interface circuit includes a single register.
17. The sub-system of claim 14 , wherein the stack includes a plurality of interface circuits.
18. A method, comprising:
interfacing a plurality of physical memory circuits and a system;
simulating at least one virtual memory circuit; and
performing a power management operation in association with only a portion of the at least one virtual memory circuit.
19. A system, comprising:
a plurality of physical memory circuits; and
an interface circuit in communication with the physical memory circuits and a system, the interface circuit operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit and performing a power management operation in association with only a portion of the at least one virtual memory circuit.