Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits

1. A sub-system, comprising:

a plurality of interface circuits in communication with a plurality of memory circuits and a system, the interface circuits operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits;

wherein the interface circuits are further operable for simulating at least one virtual memory circuit;

wherein the interface circuits are positioned on a dual in-line memory module (DIMM).

2. The sub-system of claim 1 , wherein the power management operation is initiated by the interface circuits autonomously.

3. The sub-system of claim 1 , wherein the power management operation is initiated by at least one non-power management signal.

4. The sub-system of claim 3 , wherein the non-power management signal includes a control signal.

5. The sub-system of claim 4 , wherein the control signal is selected from the group consisting of an address signal and a data signal.

6. The sub-system of claim 4 , wherein the control signal is associated with an operation selected from the group consisting of an activate operation, a precharge operation, a write operation, a read operation, a mode register write operation, a mode register read operation, and a refresh operation.

7. The sub-system of claim 1 , wherein the power management operation is initiated in response to at least one non-power related state of one or more of the memory circuits.

8. The sub-system of claim 7 , wherein the at least one state is selected from the group consisting of a predetermined combination of commands issued to the one or more of the memory circuits, a predetermined pattern of commands issued to the one or more of the memory circuits, and a predetermined absence of commands issued to the one or more of the memory circuits.

9. The sub-system of claim 1 , wherein the power management operation is performed in association with only a portion of the virtual memory circuit.

10. The sub-system of claim 1 , wherein the at least one virtual memory circuit includes a single virtual memory circuit.

11. The sub-system of claim 1 , wherein the power management operation includes a power saving operation.

12. The sub-system of claim 1 , wherein the interface circuits are intelligent.

13. The sub-system of claim 1 , wherein the interface circuits are selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

14. The sub-system of claim 1 , wherein the interface circuits and the memory circuits take the form of a stack.

15. A method, comprising:

interfacing a plurality of memory circuits and a system; and

autonomously performing a power management operation in association with at least a portion of the memory circuits;

wherein a plurality of interface circuits interface the memory circuits and the system, the interface circuits simulating at least one virtual memory circuit;

wherein the interface circuits are positioned on a dual in-line memory module (DIMM).

16. A system, comprising:

a plurality of memory circuits; and

a plurality of interface circuits in communication with the memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits;

wherein the interface circuits are further operable for simulating at least one virtual memory circuit;

wherein the interface circuits are positioned on a dual in-line memory module (DIMM).