MEMORY DEVICE WITH EMULATED CHARACTERISTICS
A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
1 . A sub-system, comprising:
an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits, the interface circuit including emulation logic for emulating at least one memory circuit of a second number.
2 . The sub-system of claim 1 , wherein the second number is less than the first number.
3 . The sub-system of claim 2 , wherein the second number is one.
4 . The sub-system of claim 1 , wherein the emulation logic emulates at least one memory circuit with a first memory capacity that is different than a second memory capacity of at least one of the plurality of memory circuits.
5 . The sub-system of claim 1 , wherein the interface circuit is adapted for communication with all of the address or control signals of the memory circuits.
6 . The sub-system of claim 1 , wherein the interface circuit is adapted for communication with a majority of the address signals of the memory circuits.
7 . The sub-system of claim 1 , wherein the interface circuit is adapted for communication with a majority of the control signals of the memory circuits.
8 . The sub-system of claim 1 , wherein the emulation includes an electrical emulation.
9 . The sub-system of claim 1 , wherein the emulation includes a logical emulation.
10 . The sub-system of claim 1 , wherein the interface circuit includes a buffer chip.
11 . The sub-system of claim 1 , wherein the interface circuit is positioned on a dual in-line memory module (DIMM).
12 . The sub-system of claim 11 , wherein the DIMM includes a small outline-DIMM (SO-DIMM).
13 . The sub-system of claim 11 , wherein the DIMM includes a fully buffered-DIMM (FB-DIMM).
14 . The sub-system of claim 11 , wherein the DIMM includes a registered-DIMM (R-DIMM).
15 . The sub-system of claim 1 , wherein the memory circuits each include dynamic random access memory (DRAM).
16 . The sub-system of claim 15 , wherein the memory circuits each include a monolithic DRAM.
17 . The sub-system of claim 16 , wherein the memory circuits are stacked.
18 . The sub-system of claim 16 , wherein the memory circuits and the interface circuit are stacked.
19 . A method, comprising:
interfacing a majority of address or control signals of a first number of memory circuits and a system; and
emulating at least one memory circuit of a second number.
20 . An apparatus, comprising:
a first number of memory circuits; and
an interface circuit in communication with the memory circuits, the interface circuit including emulation logic for emulating at least one memory circuit of a second number;
wherein the interface circuit interfaces a majority of address or control signals of the memory circuits.