Method and Apparatus For Refresh Management of Memory Modules
One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices
1 . A method for generating staggered refresh commands for two or more memory devices, the method comprising:
analyzing a connectivity for transmitting refresh signals between an interface circuit and the two or more memory devices;
calculating a timing for issuing staggered refresh command to the two or more memory devices based on a refresh command received from a memory controller and the analyzed connectivity; and
asserting the staggered refresh commands to the two or more memory devices at the calculated times.
2 . The method of claim 1 , wherein the step of analyzing is performed statically, prior to applying power to a system device coupled to the memory controller.
3 . The method of claim 1 , wherein the step of analyzing is performed dynamically, after applying power to a system device coupled to the memory controller.
4 . The method of claim 1 , wherein the step of analyzing is performed periodically, after applying power to a system device coupled to the memory controller.
5 . The method of claim 4 , wherein the step of analyzing comprises determining characteristics of a configuration of the connectivity between the interface circuit and the two or more memory devices.
6 . The method of claim 5 , wherein the interface circuit is directly coupled to a memory module, and the step of analyzing further comprises determining a configuration of the memory module.
7 . The method of claim 6 , wherein the memory module comprises a dual in-line memory module.
8 . The method of claim 6 , wherein the step of analyzing further comprises determining the manufacturer of the two or more memory devices.
9 . The method of claim 8 , wherein the step of analyzing further comprises determining an operating temperature.
10 . The method of claim 8 , wherein the step of calculating comprises calculating a refresh signal timing for an initialization phase.
11 . The method of claim 10 , wherein the step of calculating further comprises calculating a refresh signal timing for an operation phase.
12 . The method of claim 1 , wherein the steps of calculating and asserting are performed asynchronously.
13 . The method of claim 1 , wherein the steps of analyzing, calculating and asserting are performed by logic included in the interface circuit.
14 . The method of claim 1 , wherein at least one of the steps of analyzing, calculating and asserting is performed by logic included in the interface circuit, and the other steps are performed by an intelligent buffer coupled to the interface circuit.
15 . The method of claim 1 , wherein the step of analyzing comprises performing a series of analog and logic tests to measure pin characteristics of the two or more memory devices.
16 . The method of claim 15 , wherein the measured pin characteristics include a timing of response related to when voltage change crosses logical 1 and logical 0 thresholds.
17 . The method of claim 15 , wherein the measured pin characteristics include a timing response related to a peak detected voltage change.
18 . The method of claim 17 , wherein the measured pin characteristics include a signal response ringing.
19 . A computer-readable medium including instructions that when executed by a processing unit cause the processing unit to generate staggered refresh commands for two or more memory devices, by performing the steps of:
analyzing a connectivity for transmitting refresh signals between an interface circuit and the two or more memory devices;
calculating a timing for issuing staggered refresh command to the two or more memory devices based on a refresh command received from a memory controller and the analyzed connectivity; and
asserting the staggered refresh commands to the two or more memory devices at the calculated times.
20 . The computer-readable medium of claim 19 , wherein the step of analyzing is performed statically, prior to applying power to a system device coupled to the memory controller.
21 . The computer-readable medium of claim 19 , wherein the step of analyzing is performed dynamically, after applying power to a system device coupled to the memory controller.
22 . The computer-readable medium of claim 19 , wherein the step of analyzing is performed periodically, after applying power to a system device coupled to the memory controller.
23 . The computer-readable medium of claim 22 , wherein the step of analyzing comprises determining characteristics of a configuration of the connectivity between the interface circuit and the two or more memory devices.
24 . The computer-readable medium of claim 23 , wherein the interface circuit is directly coupled to a memory module, and the step of analyzing further comprises determining a configuration of the memory module.
25 . The computer-readable medium of claim 24 , wherein the memory module comprises a dual in-line memory module.
26 . The computer-readable medium of claim 25 , wherein the step of analyzing further comprises determining the manufacturer of the two or more memory devices.
27 . The computer-readable medium of claim 26 , wherein the step of analyzing further comprises determining an operating temperature.
28 . The computer-readable medium of claim 26 , wherein the step of calculating comprises calculating a refresh signal timing for an initialization phase.
29 . The computer-readable medium of claim 28 , wherein the step of calculating further comprises calculating a refresh signal timing for an operation phase.
30 . The computer-readable medium of claim 19 , wherein the steps of calculating and asserting are performed asynchronously.