Power saving system and method for use with a plurality of memory circuits

1. A method, comprising:

identifying a first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and

in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;

wherein the first plurality of memory circuits is a rank.

2. A sub-system, comprising:

a component in communication with a plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one of the plurality of memory circuits that is not accessed by the system;

wherein the plurality of memory circuits is a rank.

3. A method of managing power in an electronic system including a memory, the memory including a first plurality of memory circuits, the method comprising:

identifying the first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and

in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;

wherein the first plurality of memory circuits is a rank.

4. The method of claim 3 , wherein the power saving operation comprises:

a power down operation.

5. The method of claim 4 , wherein the power down operation comprises:

a precharge power down operation.

6. The method of claim 3 , wherein the at least one memory circuit has a clock enable input, the method further comprising:

initiating the power saving operation by utilizing the clock enable input of the at least one memory circuit.

7. The method of claim 6 , wherein utilizing the clock enable input comprises:

de-asserting the clock enable input of the at least one memory circuit.

8. The method of claim 6 , wherein the identifying comprises:

determining whether a page is being accessed in at least one of the plurality of memory circuits.

9. The method of claim 3 , wherein the system further includes a component, and wherein:

at least one of the identifying and the initiating is carried out utilizing the component.

10. The method of claim 9 , wherein the component includes an advanced memory buffer (AMB).

11. The method of claim 9 , wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).

12. The method of claim 9 , wherein the component includes a memory controller.

13. The method of claim 9 , wherein the component includes a register.

14. The method of claim 3 , wherein the memory includes a number (x) of the memory circuits, the method further comprising:

continuously subjecting a lesser number of the memory circuits to the power saving operation.

15. The method of claim 14 , wherein the lesser number comprises x−1.

16. The method of claim 3 , wherein the system further includes an interface circuit coupled to interface the plurality of memory circuits and the system, and wherein:

at least one of the identifying and the initiating is carried out utilizing the interface circuit.

17. The method of claim 3 , wherein the memory circuits each includes dynamic random access memory (DRAM).

18. The method of claim 17 , wherein the DRAM of each of the memory circuits each comprises a monolithic DRAM.

19. The method of claim 18 , wherein the memory circuits are stacked.

20. The method of claim 18 , wherein the memory circuits and the interface circuit are, stacked.

21. An apparatus for use with an electronic system, the apparatus comprising:

a first plurality of memory circuits; and

a component in communication with the first plurality of memory circuits and the system, the component operable to initiate a power savings operation in association with at least one memory circuit of a second plurality of memory circuits that is not accessed by the system, the first plurality of memory circuits including the second plurality of memory circuits;

wherein the first plurality of memory circuits is a rank.

22. A method of operating a system, the system including a memory including “x” memory circuits, the method comprising:

accessing “p” of the memory circuits;

while the “p” memory circuits are being accessed, performing a power saving operation on “q” others of the memory circuits;

wherein “p”+“q”<=“x”;

wherein the “x” memory circuits is a rank.

23. The method of claim 22 , wherein performing the power saving operation comprises:

de-asserting a clock enable input of the “q” memory circuits.

24. The method of claim 1 , wherein initiating the power saving operation utilizes a clock enable input of the at least one memory circuit.

25. A method, comprising:

identifying one or more portions of at least one of a plurality of memory circuits that is not currently being accessed, the plurality of memory circuits being at least part of a rank; and

in response to the identification of the one or more portions of the at least one memory circuit, initiating a power saving operation in association with the one or more portions of the at least one memory circuit.

26. An apparatus comprising:

a first plurality of memory circuits; and

a component in communication with the first plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one memory circuit of a second plurality of memory circuits that is not accessed by the system, the first plurality of memory circuits including the second plurality of memory circuits;

wherein the first plurality of memory circuits is a rank;

wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).

27. A method of managing power in an electronic system including a memory, the memory including a first plurality of memory circuits, the method comprising:

identifying the first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and

in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;

wherein the first plurality of memory circuits is a rank;

wherein the system further includes a component, and at least one of the identifying and the initiating is carried out utilizing the component;

wherein the component includes a register.