Duty ratio adjustment
View Patent ↗There is disclosed a duty ratio adjustment for adjusting the duty ratio of an input clock signal. First and second one-shot pulse generation circuits respectively detect rising/tailing edges of an external input signal and output pulse signals of constant widths. Third and fourth one-shot pulse generation circuits respectively detect rising/tailing edges of an output signal from the delay circuit and output pulse signals. A selector circuit outputs the pulse signals that are output from the third and second one-shot pulse generation circuits as H edge/L edge generation clock signals, when the L width is broadened, and outputs the pulse signals that are output from the first and fourth one-shot pulse generation circuits as H edge/L edge generation clock signals, when the H width is broadened. A waveform synthesis circuit outputs a signal that changes to a high level between the timing during which the high edge generation signal is output from the selector circuit and the timing during which the low edge generation signal is output from the selector circuit, as an internal clock signal.
1. A semiconductor device comprising: a duty ratio adjustment circuit for adjusting a duty ratio of an input clock signal that is input from the outside and for outputting the input clock signal as an internal clock signal, wherein said duty ratio adjustment circuit comprises: a first one-shot pulse generation circuit for detecting a rising edge of said input clock signal and for outputting a pulse signal; a second one-shot pulse generation circuit for detecting a tailing edge of said input clock signal and for outputting a pulse signal; a delay circuit for delaying said input clock signal by a preset delay time and for outputting said input clock signal; a third one-shot pulse generation circuit for detecting a rising edge of an output signal from said delay circuit and for outputting a pulse signal; a fourth one-shot pulse generation circuit for detecting a tailing edge of the output signal from said delay circuit and for outputting a pulse signal; a selector circuit, upon receipt of instructions that a low level width of said input clock signal be broadened, for outputting the pulse signal output from said third one-shot pulse generation circuit as a high edge generation clock signal and for outputting the pulse signal output from said second one-shot pulse generation circuit as a low edge generation clock signal, and, upon receipt of instructions that a high level width of said input clock signal be broadened, for outputting the pulse signal output from said first one-shot pulse generation circuit as a high edge generation clock signal and for outputting the pulse signal output from said fourth one-shot pulse generation circuit as a low edge generation clock signal; and a waveform synthesis circuit for outputting a signal that changes to a high level between the dining during which the high edge generation signal is output from said selector circuit and the timing during which the low edge generation signal is output from said selector circuit, as an internal clock signal.
2. The semiconductor device according to claim 1 , wherein in said delay circuit, a delay amount can be set in accordance with a delay amount adjustment signal from the outside.
3. The semiconductor device according to claim 1 , wherein in said delay circuit, a delay amount during rising and a delay amount during tailing, can be independently set in accordance with a delay amount adjustment signal from the outside.