Bond pad for wafer and package for CMOS imager
View Patent ↗An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
1. A method of forming an electronic package including a semiconductor chip having a plurality of electrically connected layers arranged on a substrate and at least one bond pad positioned on an upper surface of said semiconductor chip, wherein said method comprises equipping said electronic package with structure extending between said at least one bond pad and said substrate for protecting electrical connections and components contained therein from an ingress of moisture and contaminants, wherein said protective structure includes an edge seal and a crack stop each forming a ring-shaped arrangement extending in a mutually spaced relationship about the periphery of said at least one bond pad, wherein the at least one bond pad comprises a bond pad array, and wherein said peripheral crack stop extends externally about said bond pad array, and said edge seal extends interiorly of said bond pad array; and wherein a through-via for packaging leads extends though said substrate layer and active layers of said semiconductor chip to said bond pads.
2. A method as claimed in claim 1 , wherein said edge seat extends partially about an edge portion of the respective bond pads in an active layer, which is located on said substrate layer.
3. A method as claimed in claim 1 , wherein said bond pad array is located on said substrate layer, and at least one probe pad comprises a top layer of said electronic package, said edge seal having an upper portion and a lower portion so as to facilitate connection of said bond pads to an interior of said semiconductor chip in the absence of being electrically connected to said edge seal.
4. A method as claimed in claim 1 , wherein said edge seal and crack stop inhibit the ingress of moisture and contaminants from a rear edge and sides of said electronic package.
5. A method as claimed in claim 4 , wherein said crack stop prevents the propagation of cracks and fissures into said electronic package resulting from dicing cuts separating said semiconductor chip from a wafer.