IP Library › Patent Application 11466233
Patent Application
App. No. 11/466,233

Carbon Nanotube Transistor Voltage Converter Circuit

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Quick Facts
Patent No.
US None
App. No.
11/466,233
Abstract

A voltage converter circuit includes one or more single-walled carbon nanotube transistors, capable of handling relatively high amounts of current. The transistors are formed using a porous structure which has a number of single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another porous material. The circuit will be especially suited for power applications, including use in portable electronic devices such as notebook computers, MP3 players, mobile phones, digital cameras, personal digital assistants, and other battery-operated devices.

Claims (45)

1 . A circuit comprising:

a voltage input node;

a voltage output node;

a first single-walled carbon nanotube transistor coupled between the voltage input node and a first node, wherein the first single-walled carbon nanotube transistor comprises a plurality of single-walled carbon nanotubes between a first gate region and a second gate region;

a second single-walled carbon nanotube transistor coupled between the first node and ground; and

an inductor coupled between the first node and the voltage output node.

2 . The circuit of claim 1 wherein the first and second single-walled carbon nanotube transistors are formed on the same structure.

3 . The circuit of claim 1 further comprising:

a capacitor between the first node and ground.

4 . The circuit of claim 3 further comprising:

a resistor between the first node and ground.

5 . The circuit of claim 1 wherein the first and second single-walled carbon nanotube transistors do not have bulk node connections.

6 . The circuit of claim 1 wherein the first and second gate regions are electrically coupled together.

7 . The circuit of claim 1 wherein the first and second gate regions are parallel to each other, extending a length A in an X direction and separated by a gap B in a Y direction, and the single-walled carbon nanotubes extend in a Z direction, perpendicular to both the X and Y directions.

8 . The circuit of claim 7 wherein in the gap B, there are a plurality of single-walled carbon nanotubes.

9 . The circuit of claim 7 wherein the first and second gate regions have a width C, and there are a plurality of carbon nanotubes below the gate regions that are not effective.

10 . The circuit of claim 7 wherein the first and second gate regions further have a thickness D in the Z direction.

11 . The circuit of claim 1 wherein the first single-walled carbon nanotube transistor is an enhancement mode transistor.

12 . The circuit of claim 1 wherein the first single-walled carbon nanotube transistor is a depletion mode transistor.

13 . The circuit of claim 1 wherein the first single-walled carbon nanotube transistor is an n-type transistor.

14 . The circuit of claim 1 wherein the first single-walled carbon nanotube transistor is a p-type transistor.

15 . A circuit comprising:

a voltage input node;

a voltage output node;

a first single-walled carbon nanotube device coupled between the voltage input node and a first node, wherein the first single-walled carbon nanotube device comprises a plurality of channel regions formed using a plurality of single-walled carbon nanotubes; and

an inductor coupled between the first node and the voltage output node.

16 . The circuit of claim 16 wherein the first single-walled carbon nanotube device comprises first and second gate regions, extending parallel to each other a length A in an X direction and separated by a gap B in a Y direction, and the single-walled carbon nanotubes extend in a Z direction, perpendicular to both the X and Y directions.

17 . The circuit of claim 16 further comprising:

a second device coupled between the first node and a reference node.

18 . The circuit of claim 17 wherein the second device comprises single-walled carbon nanotubes.

19 . The circuit of claim 17 wherein the second device comprises a diode.

20 . A notebook computer system comprising a circuit as recited in claim 15 .

21 . The circuit of claim 1 wherein the first gate region of the first single-walled carbon nanotube transistor is formed in a first trench.

22 . The circuit of claim 1 wherein the first gate region of the first single-walled carbon nanotube transistor is formed in a first trench and the second gate region of the first single-walled carbon nanotube transistor is formed in a second trench, different from the first trench.

23 . The circuit of claim 22 wherein between the first and second gate regions are at least two single-walled carbon nanotubes.

24 . The circuit of claim 22 wherein the first gate region and second gate region are electrically coupled together.

25 . The circuit of claim 7 wherein the first gate region extends a distance C in the Z direction.

26 . The circuit of claim 7 wherein the first gate region is formed in a first trench extending a distance C in the Z direction.

27 . The circuit of claim 1 wherein a first voltage is applied to the voltage input node to cause a current to pass through carbon nanotubes of the first single-walled carbon nanotube transistor to burn off metallic carbon nanotubes.

28 . The circuit of claim 27 wherein a second voltage is applied to the first gate region to prevent single-walled carbon nanotubes from burning off.

29 . The circuit of claim 1 wherein the first and second gate regions of the first single-walled carbon nanotube transistor are not coupled to a gate region of the second single-walled carbon nanotube transistor.

30 . The circuit of claim 15 wherein the first single-walled carbon nanotube device comprises a first gate region formed in a first trench.

31 . The circuit of claim 17 wherein the first single-walled carbon nanotube device comprises a first gate region formed in a first trench, the second device comprises a second gate region formed in a second trench, and between the first and second gate regions are at least two single-walled carbon nanotubes.

32 . The circuit of claim 31 wherein the first and second gate regions are not coupled together.

33 . The circuit of claim 15 wherein a first voltage is applied to the voltage input node to cause a current to pass through carbon nanotubes of the first single-walled carbon nanotube device to burn off metallic carbon nanotubes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2009
From: ATOMATE CORPORATION
To: ETAMOTA CORPORATION
Reel/Frame 023660/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2006
From: TOMBLER, JR., THOMAS W.; LIM, BRIAN Y.
To: ATOMATE CORPORATION
Reel/Frame 018154/0040 →