Random seed stability with fuses
View Patent ↗A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
1. A circuit for stabilizing soft bits in a bit stream, the circuit comprising:
a first register adapted to receive an initial read of the bit stream,
a second register adapted to receive a subsequent read of the bit stream,
a comparator adapted to compare the initial read of the bit stream to the subsequent read of the bit stream,
a third register adapted to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and
an accumulator adapted to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
2. The circuit of claim 1 , further comprising a logic circuit adapted to send the initial read of the bit stream to the first register and reset the accumulator after an initialization, and send the subsequent read of the bit stream to the second register.
3. The circuit of claim 1 , wherein the comparator is an XOR cell.
4. The circuit of claim 1 , further comprising a broken seed detector adapted to determine whether the bit stream is stable to within a statistically desirable probability for use as at least one of a unique identification string and an encryption key.
5. An integrated circuit having a circuit for stabilizing soft bits in a bit stream, the circuit comprising:
a first register adapted to receive an initial read of the bit stream,
a second register adapted to receive a subsequent read of the bit stream,
a comparator adapted to compare the initial read of the bit stream to the subsequent read of the bit stream,
a third register adapted to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and
an accumulator adapted to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
6. The integrated circuit of claim 5 , further comprising a logic circuit adapted to send the initial read of the bit stream to the first register and reset the accumulator after an initialization, and send the subsequent read of the bit stream to the second register.
7. The integrated circuit of claim 5 , wherein the comparator is an XOR cell.
8. The integrated circuit of claim 5 , further comprising a broken seed detector adapted to determine whether the bit stream is stable to within a statistically desirable probability for use as at least one of a unique identification string and an encryption key.
9. A method of stabilizing soft bits in a bit stream, the method comprising the steps of:
receiving an initial read of the bit stream,
receiving a subsequent read of the bit stream,
comparing the initial read of the bit stream to the subsequent read of the bit stream,
producing a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and
receiving the comparison string for multiple subsequent reads of the bit stream, and tracking positions of all soft bits detected during the multiple subsequent reads.