Clock and data recovery
A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.
1. A circuit, comprising:
a retimer;
a clock recovery circuit to provide a clock signal to the retimer; and
an adjustable delay to provide a delayed version of an input signal to the retimer;
wherein when in a first mode,
the adjustable delay causes a pre-selected delay in the input signal and
the clock recovery circuit dynamically selects a clock phase to generate the clock signal.
2. The circuit of claim 1 , wherein when in a second mode,
the adjustable delay dynamically adjusts the delayed version of the input signal and
the clock recovery circuit outputs the clock signal having a pre-selected clock phase.
3. The circuit of claim 2 , further comprising;
a control circuit coupled to the clock recovery circuit and the adjustable delay to switch between the first mode and the second mode.
4. The circuit of claim 3 , wherein when the control circuit provides a signal to switch from the first mode to the second mode, a current clock phase in the first mode is selected as the pre-selected clock phase in the second mode.
5. The circuit of claim 4 , wherein when the control circuit provides a signal to switch from the second mode to the first mode, a pre-determined constant delay is selected as the pre-selected delay in the first mode.
6. The circuit of claim 4 , wherein when the control circuit provides a signal to switch from the second mode to the first mode, a current delay in the second mode is selected as the pre-selected delay in the first mode.
7. The circuit of claim 3 , further comprising:
a phase detector coupled to an output of the retimer;
wherein the clock recovery circuit and an adjustable delay receive an output of the phase detector as input.
8. The circuit of claim 7 , wherein the phase detector comprises an Alexander phase detector.
9. The circuit of claim 7 , wherein the clock recovery circuit comprises:
a loop to generate multiple clocks from a reference clock;
a state machine coupled to the phase detector to determine a control signal from the output of the phase detector; and
a multiplexer coupled to the state machine and the loop to select the clock signal from the multiple clock according to control signal.
10. The circuit of claim 9 , wherein the loop comprises a phase lock loop or a delay look loop.
11. The circuit of claim 7 , wherein the clock recovery circuit comprises:
a loop to generate multiple clocks from a reference clock;
a state machine coupled to the phase detector to determine a control signal from the output of the phase detector; and
an interpolator coupled to the state machine and the loop to generate the clock signal from the multiple clock according to control signal.
12. The circuit of claim 11 , wherein when switching to the second mode, the state machine is switched to maintain a current state regardless of the output of the phase detector.
13. The circuit of claim 11 , wherein the adjustable delay is further controlled according to an output of the loop.
14. The circuit of claim 1 , wherein the retimer comprises a flip-flop.
15. A circuit having a first mode and a second mode, the circuit comprising:
a retimer;
a clock recovery circuit to provide a clock signal to the retimer, wherein when in the first mode a phase of the clock signal is adjusted according to an output of the retimer and when switching from the first mode to the second mode a current phase of the clock signal determined in the first mode is maintained and not changed in the second mode; and
an adjustable delay to provide a delayed version of an input signal to the retimer.
16. The circuit of claim 15 , wherein when in the second mode, the adjustable delay is adjusted according to the output of the retimer; and when in the first mode, the adjustable delay is not adjusted according to the output of the retimer.
17. The circuit of claim 16 , further comprising:
a phase detector coupled to the clock recovery circuit and the adjustable delay;
wherein the clock recovery circuit is at least controlled by an output of the phase detector in the second mode; and
the adjustable delay is at least controlled by the output of the phase detector in the first mode.
18. A circuit, comprising:
a mode control to provide a first control signal for a first mode and a second signal for a second mode;
a retimer;
a phase detector coupled to an output of the retimer;
a clock recovery circuit coupled to the mode control to provide a clock signal to the retimer, wherein when in the first mode the clock signal is adjusted according to an output of the phase detector and when in the second mode the clock signal is not adjusted;
an adjustable delay to generate a delayed version of an input signal; and
a multiplexer coupled to the mode control to provide the delay version of the input signal to the retimer in the second mode and provide the input signal to the retimer in the first mode.
19. The circuit of claim 18 , wherein the clock recovery circuit comprises:
a locked loop comprising a delay chain to generate multiple clocks from a reference clock;
a multiplexer coupled to the mode control;
a counter coupled to multiplexer to generate a control signal from the output of the phase detector in the first mode and maintain the control signal in the second mode; and
a circuit coupled to the counter and the loop to output the clock signal based on the multiple clock according to control signal from the counter.