Copper interconnect systems which use conductive, metal-based cap layers
View Patent ↗An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The alloy seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region.
1. A method for manufacturing a Damascene-type integrated circuit, comprising:
forming copper based interconnect using a damascene-type process;
adding a first metal-based cap to a surface of said interconnect, thereby forming a capped interconnect;
forming a dielectric layer over the capped interconnect;
forming an opening in said dielectric layer and said first metal-based cap;
removing a portion of said first metal-based cap situated in said opening;
forming a diffusion barrier in said opening by depositing a diffusion barrier in said opening and etching back said diffusion barrier such that an edge protection layer is formed;
depositing an alloy seed layer in said opening, said alloy seed layer comprising copper; and
depositing copper in said opening over said alloy seed layer.
2. The method of claim 1 , further comprising forming a diffusion barrier liner on a surface of said interconnect.
3. The method of claim 2 , wherein said diffusion barrier liner comprises Ta.
4. The method of claim 2 , wherein said diffusion barrier liner comprises Ti.
5. The method of claim 2 , wherein a concentration of Ti in said diffusion barrier liner is between 1% and 30%.
6. The method of claim 2 , wherein said diffusion barrier liner has a thickness in the range of one monolayer to 200 Angstroms.
7. The method of claim 1 , further comprising performing a planarization step using CMP prior to adding said first metal-based cap.
8. The method of claim 1 , wherein said first metal-based cap is formed using an electroless Co-based alloy.
9. The method of claim 1 , further comprising forming at least one dielectric diffusion barrier over said dielectric layer.
10. The method of claim 1 , wherein said removing a portion of the first metal-based cap is done using argon bombardment.
11. The method of claim 1 , wherein said removing a portion of the first metal-based cap is done using backsputter cleaning.
12. The method of claim 1 , further comprising passivating copper deposited in said opening over said alloy seed layer using a metal more noble than copper.
13. The method of claim 12 , wherein said metal more noble than copper forms a film of thickness from 1 monolayer to 50 Angstroms.
14. The method of claim 1 , wherein said etching back is anisotropic.
15. The method of claim 1 , wherein said alloy seed layer further comprises at least one of Ta and Cr.
16. The method of claim 1 , wherein said copper deposited in said opening over said alloy seed layer is a copper alloy.
17. The method of claim 1 , further comprising adding a second metal-based cap over said copper in said opening.