Method of making self-aligned split gate memory cell
A method for forming a split gate memory cell ( 10,11 ) using a semiconductor substrate ( 12 ) includes forming a select gate structure ( 48 ) and a sacrificial structure ( 50 ) over the substrate. An opening is between the select gate structure and the sacrificial structure. The opening is lined with a storage layer ( 56,168 ). The opening is further filled with select gate material ( 58,170 ). The sacrificial structure is removed after filling the opening with the select gate material.
1. A method for forming a split gate memory cell using a semiconductor substrate, comprising: forming a first gate structure and a sacrificial structure over the semiconductor substrate, each of the first gate structure and the sacrificial structure including a nitride layer overlying the semiconductor substrate, wherein forming the first gate structure and the sacrificial structure includes forming an opening between the first gate structure and the sacrificial structure, wherein forming the first gate structure, the sacrificial structure, and the opening further includes using a single masking step which lithographically defines both (i) a gate length of the first gate structure and (ii) a gate length of a second gate structure yet to be formed, wherein the gate length of the second gate structure is lithographically defined by the opening; lining the opening with a layer; and filling the lined opening with a gate material of the second gate structure, wherein the first and second gate structures comprise one of (i) a select gate structure and a control gate structure, respectively, further wherein the layer comprises a storage layer and (ii) a control gate structure and a select gate structure, respectively, further wherein the layer comprises a dielectric layer; planarizing the gate material down to the nitride layer; thermally oxidizing an exposed top surface of the planarized gate material; and removing the sacrificial structure via a wet etch, wherein the thermally oxidized top surface of the planarized gate material protects underlying gate material during the wet etch removal of the sacrificial structure.
2. A method of claim 1 , wherein the step of removing the sacrificial structure removes the sacrificial structure from over a source area in the semiconductor substrate, further comprising: implanting into the source area to form a source region in the semiconductor substrate.
3. The method of claim 2 , further comprising providing a sidewall spacer around the source area prior to the step of implanting into the source area.
4. The method of claim 2 , wherein the step of filling the opening comprises:
depositing a layer of polysilicon; and
chemical mechanical polishing the polysilicon layer.
5. The method of claim 1 , further comprising siliciding a top surface of the select gate structure and a top surface of the control gate structure.
6. The method of claim 1 , wherein the step of forming further comprises forming a sacrificial drain structure over a drain area of the semiconductor substrate adjacent to the select gate structure.
7. The method of claim 6 further comprising removing the sacrificial drain structure.
8. The method of claim 7 , further comprising implanting into the drain area to form a drain region.
9. The method of claim 8 , wherein the step of removing the sacrificial structure removes the sacrificial structure form over a source area in the semiconductor substrate further comprising: implanting into the source area to form a source region in the semiconductor substrate at a different time than the step of implanting into the drain region.
10. The method of claim 6 , wherein the step of forming is further characterized as forming the sacrificial drain structure after the step of lining the opening.
11. The method of claim 6 , wherein the step of forming is further characterized as forming the sacrificial drain structure before the step of lining the opening.
12. The method of claim 1 , wherein the step of lining is further characterized by the storage layer comprising nanocrystals.
13. A method of forming a memory cell having a control gate, a select gate, a source, and a drain, comprising: providing a semiconductor substrate; forming a first gate structure and a first sacrificial structure over the semiconductor substrate, each of the first gate structure and the first sacrificial structure including a nitride layer overlying the semiconductor substrate, wherein forming the first gate structure and the first sacrificial structure includes forming an opening between the first gate structure and the first sacrificial structure, wherein forming the first gate structure, the first sacrificial structure, and the opening further includes using a single masking step which lithographically defines both (i) a gate length of the first gate structure and (ii) a gate length of a second gate structure yet to be formed, wherein the gate length of the second gate structure is lithographically defined by the opening; lining the opening with a layer; and forming the second gate structure in the opening after the step of lining, wherein the first and second gate structures comprise one of (i) a select gate and a control gate, respectively, further wherein the layer comprises a storage layer and (ii) a control gate and a select gate, respectively, further wherein the layer comprises a dielectric layer; planarizing a gate material of the second gate structure down to the nitride layer; thermally oxidizing an exposed top surface of the planarized gate material; removing the first sacrificial structure via a wet etch, wherein the thermally oxidized top surface of the planarized gate material protects underlying gate material during the wet etch removal of the first sacrificial structure; forming the source in the semiconductor substrate adjacent to the control gate; and forming the drain in the semiconductor substrate adjacent to the select gate.
14. The method of claim 13 , wherein: the steps of forming the source comprises performing a first implant; the steps of forming the drain comprises performing a second implant at a different time than the first implant; and the step of lining the opening is further characterized as lining the opening with one selected from the group of (i) nanocrystals, in connection with the first gate structure comprising the select gate and the second gate structure comprising the control gate and (ii) dielectric, in connection with the first gate structure comprising the control gate and the second gate structure comprising the select gate.
15. A method of claim 14 , further comprising: forming a second sacrificial structure over a source/drain area of the semiconductor substrate adjacent to the first gate structure; and removing the second sacrificial structure prior to the step of forming the source/drain in the source/drain area.
16. The method of claim 13 further comprising:
siliciding a top surface of the source, a top surface of the drain, a top surface of the select gate, and a top surface of the control gate.