Semiconductor device and production method thereof
View Patent ↗A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
1. A semiconductor device, comprising:
a silicon substrate having a channel region;
a gate electrode formed over the silicon substrate corresponding to the channel region with a gate insulating film in between;
a first side wall insulating film formed on side walls of the gate electrode;
a second side wall insulating film formed on side surfaces of the first side wall;
a source extension region and a drain extension region formed from diffusion regions having a first conductivity, said diffusion regions being formed in the silicon substrate on sides of the gate electrode to sandwich the channel region;
a source region and a drain region formed from diffusion regions having the first conductivity, said diffusion regions being formed in the silicon substrate outside the second side wall insulating film and in contact with the source extension region and the drain extension region, respectively; and
a semiconductor mixed crystal layer formed in the silicon substrate outside the second side wall insulating film and epitaxially grown over the silicon substrate;
wherein
the semiconductor mixed crystal layer is formed from a SiGe mixed crystal when the first conductivity is p-type, or from a SiC mixed crystal when the first conductivity is n-type,
the semiconductor mixed crystal layer includes an impurity having the first conductivity,
the semiconductor mixed crystal layer is grown to a height different from an interface between the silicon substrate and the gate insulating film, and the semiconductor mixed crystal layer has an extended portion between a bottom surface of the second side wall insulating film and a surface of the silicon substrate, said extended portion being in contact with a portion of one of the source extension region and the drain extension region, said extended portion having a ton surface thereof in contact with the bottom surface of the second side wall insulating film, and
the source extension region and the drain extension region include the same impurity as an impurity in the extended portion, and a concentration of the impurity in the source extension region and the drain extension region is a maximum at the extended portion and decreases from a surface of the silicon substrate along a depth direction of the silicon substrate.
2. The semiconductor device as claimed in claim 1 , wherein the source extension region and the drain extension region are formed by diffusing the impurity in the extended portion.
3. The semiconductor device as claimed in claim 1 , wherein
a region below the gate insulating film on an inner side of the source extension region and the drain extension region is a well region having a second conductivity opposite to the first conductivity, and
in a region deeper than the source extension region and the drain extension region, a concentration of an impurity having the second conductivity approximately equals a concentration of an impurity in the well region.
4. The semiconductor device as claimed in claim 1 , wherein
the semiconductor device is a p-channel MOS transistor in which the first conductivity is p-type, and the semiconductor mixed crystal layer is formed from a SiGe mixed crystal layer including a p-type impurity, and
the source extension region and the drain extension region include the same type of impurity as the extended portion.
5. The semiconductor device as claimed in claim 1 , wherein
the semiconductor device is an n-channel MOS transistor in which the first conductivity is of n-type, and the semiconductor mixed crystal layer is formed from a SiC mixed crystal layer including an n-type impurity, and
the source extension region and the drain extension region include the same type of impurity as the extended portion.
6. The semiconductor device as claimed in claim 1 , wherein
a thickness of the extended portion is in a range from 5 nm to 20 nm.
7. The semiconductor device as claimed in claim 1 , wherein
a third side wall insulating film is formed between one of two opposite side walls of the gate electrode and the first side wall insulating film, said third side wall insulating film being in contact with the surface of the silicon substrate and covering a side wall of the gate insulating film,
the third side wall insulating film and the first side wall insulating film are formed from different insulating materials each having etching selectivity.
8. The semiconductor device as claimed in claim 1 , wherein
the silicon substrate has a (100) plane as a principal plane; and
the gate electrode extends over the silicon substrate approximately in a <110> direction or approximately in a <100> direction.
9. The semiconductor device as claimed in claim 1 , wherein the semiconductor mixed crystal layer is formed in contact with an outer surface of the second side wall insulating film.
10. The semiconductor device as claimed in claim 1 , wherein side surfaces of the semiconductor mixed crystal layer include facets at predetermined angles relative to a principal plane of the silicon substrate.
11. The semiconductor device as claimed in claim 1 , wherein the first side wall insulating film and the second side wall insulating film are formed from different insulating materials each having etching selectivity.
12. A semiconductor device, comprising:
a silicon substrate having a channel region;
a gate electrode formed over the silicon substrate corresponding to the channel region with a gate insulating film in between;
a first side wall insulating film formed on side walls of the gate electrode;
a second side wall insulating film formed on side surfaces of the first side wall;
a source extension region and a drain extension region formed from diffusion regions having a first conductivity, said diffusion regions being formed in the silicon substrate on sides of the gate electrode to sandwich the channel region;
a source region and a drain region formed from diffusion regions having the first conductivity, said diffusion regions being formed in the silicon substrate outside the second side wall insulating film and in contact with the source extension region and the drain extension region, respectively; and
a semiconductor mixed crystal layer formed in the silicon substrate outside the second side wall insulating film and epitaxially grown over the silicon substrate;
wherein
the semiconductor mixed crystal layer is formed from a SiGe mixed crystal when the first conductivity is p-type, or from a SiC mixed crystal when the first conductivity is n-type,
the semiconductor mixed crystal layer includes an impurity having the first conductivity,
the semiconductor mixed crystal layer is grown to a height different from an interface between the silicon substrate and the gate insulating film, and the semiconductor mixed crystal layer has an extended portion between a bottom surface of the second side wall insulating film and a surface of the silicon substrate, said extended portion being in contact with a portion of one of the source extension region and the drain extension region, said extended portion having a ton surface thereof in contact with the bottom surface of the second side wall insulating film,
a third side wall insulating film is formed between one of two opposite side walls of the gate electrode and the first side wall insulating film, said third side wall insulating film being in contact with the surface of the silicon substrate and covering a side wall of the gate insulating film, and
the third side wall insulating film and the first side wall insulating film are formed from different insulating materials each having etching selectivity.
13. The semiconductor device as claimed in claim 12 , wherein a thickness of the third side wall insulating film is approximately equal to or less than a thickness of the first side wall insulating film.
14. The semiconductor device as claimed in claim 12 , wherein the extended portion is in contact with an outer side surface of the third side wall insulating film.
15. The semiconductor device as claimed in claim 12 , wherein
a thickness of the extended portion is in a range from 5 nm to 20 nm.
16. The semiconductor device as claimed in claim 12 , wherein
the silicon substrate has a (100) plane as a principal plane; and
the gate electrode extends over the silicon substrate approximately in a <110> direction or approximately in a <100> direction.
17. The semiconductor device as claimed in claim 12 , wherein the semiconductor mixed crystal layer is formed in contact with an outer surface of the second side wall insulating film.
18. The semiconductor device as claimed in claim 12 , wherein side surfaces of the semiconductor mixed crystal layer include facets at predetermined angles relative to a principal plane of the silicon substrate.
19. The semiconductor device as claimed in claim 12 , wherein the first side wall insulating film and the second side wall insulating film are formed from different insulating materials each having etching selectivity.