Etchant, method for fabricating interconnection line using the etchant, and method for fabricating thin film transistor substrate using the etchant
View Patent ↗An etchant, a method for fabricating a multi-layered interconnection line using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant for the multi-layered line comprised of molybdenum/copper/molybdenum nitride illustratively includes 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.
1. A method for fabricating an interconnection line, the method comprising:
forming multiple layers including a buffer layer consisting of molybdenum (Mo), a copper (Cu) layer, and a corrosion prevention layer consisting of molybdenum nitride (MoN) on a substrate, wherein the Cu layer is interposed between the buffer layer and the corrosion prevention layer; and
etching the multiple layers using an etchant consisting of 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.
2. The method of claim 1 , wherein the organic acid is citric acid, the triazole-based compound is benzotriazole, and the fluoride compound is hydrofluoric acid.
3. The method of claim 1 , wherein the substrate is an insulating substrate or a semiconductor substrate.
4. The method of claim 1 , wherein the etching is performed at a temperature of 20-50° C.
5. The method of claim 1 , wherein the etching is performed using spraying.
6. The method of claim 1 , wherein the etching is performed for 50-120 seconds.
7. The method of claim 1 , wherein the etching is performed on the buffer layer, the Cu layer, and the corrosion prevention layer forming the multiple layers in a batch manner.
8. The method of claim 1 wherein the buffer layer, Cu layer and corrosion prevention layer are sequentially deposited.
9. A method for fabricating a thin film transistor (TFT) substrate, the method comprising:
forming a multi-layered gate line on a substrate and forming a gate interconnection line by etching the multi-layered gate line;
forming a gate insulating layer and a semiconductor layer on the substrate and the gate interconnection line; and
forming a multi-layered data line on the semiconductor layer and forming a data interconnection line by etching the multiple-layered data line, wherein the forming of the gate interconnection line and/or the data interconnection line comprises sequentially depositing a buffer layer consisting of molybdenum (Mo), a copper (Cu) layer, and a corrosion prevention layer consisting of molybdenum nitride (MoN) on the substrate, so that the Cu layer is interposed between the buffer layer and the corrosion prevention layer, and etching using an etchant consisting of 10-20 wt % hydrogen peroxide, 1-5 wt % organic acid, a 0.1-1 wt % triazole-based compound, a 0.01-0.5 wt % fluoride compound, and deionized water as the remainder.
10. The method of claim 9 , wherein the organic acid is citric acid, the triazole-based compound is benzotriazole, and the fluoride compound is hydrofluoric acid.
11. The method of claim 9 , wherein the etching is performed at a temperature of 20-50° C.
12. The method of claim 9 , wherein the etching is performed using spraying.
13. The method of claim 9 , wherein the etching is performed for 50-120 seconds.
14. The method of claim 9 , wherein the etching is performed on the buffer layer, the Cu layer, and the corrosion prevention layer forming the multiple layers in a batch manner.