Granted Patent B2

US 7,361,597 · App. 11/473,692 · Granted Apr 22, 2008

Abstract

Claims (34)

1. A semiconductor device comprising:

an alloy layer formed on a substrate;

a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween;

a gate insulating layer formed on the gate electrode;

a first conductive layer formed on the substrate, the source electrode, and the drain electrode;

source and drain impurity regions formed in the first conductive layer and the second conductive layer on the source electrode and the drain electrode; and

a second conductive layer and a metal silicide layer sequentially stacked on the first conductive layer, wherein the metal silicide layer covers a region above the gate electrode, the source electrode, and the drain electrode.

2. The semiconductor device of claim 1 , wherein the alloy layer is formed of a material having carbon.

3. The semiconductor device of claim 2 , wherein the alloy layer is formed of poly-germanium-carbon.

4. The semiconductor device of claim 1 , wherein the gate insulating layer is formed of a high-K dielectric layer.

5. The semiconductor device of claim 1 , wherein the metal silicide layer is formed of tungsten silicide, cobalt silicide, titanium silicide, or tantalum silicide.

6. The semiconductor device of claim 1 , wherein the first conductive layer and the second conductive layer are formed of polysilicon.

7. The semiconductor device of claim 1 , wherein the first conductive layer is formed to a height as high as a top surface of the gate insulating layer.

8. The semiconductor device of claim 1 , wherein the second conductive layer covers a region above the gate electrode, the source electrode, and the drain electrode.

9. The semiconductor device of claim 1 , wherein the gate electrode, the source electrode, and the drain electrode are formed of aluminum (Al), aluminum alloy (AlNd), Chrome (Cr) or molybdenum (Mo).

10. A method of fabricating a semiconductor device, the method comprising:

forming a poly-germanium-carbon alloy layer on a substrate;

forming a source electrode, a drain electrode, and a gate electrode on the alloy layer at predetermined intervals therebetween;

forming a gate insulating layer on a surface of the gate electrode;

forming a first conductive layer on the substrate, the gate insulating layer, the source electrode, and the drain electrode;

planarizing the first conductive layer to expose a top surface of the gate insulating layer;

forming a second conductive layer above the substrate;

selectively forming source and drain impurity regions in the first and second conductive layers; and

forming a metal silicide layer on the second conductive layer;

the method further comprising varying the size of the energy band gap of the poly-germanium-carbon layer by adjusting the amount of carbon added to poly-germanium of the poly-germanium-carbon alloy layer.

11. The method of claim 10 , further comprising:

performing a channel ion implantation in the first conductive layer.

12. The method of claim 10 , wherein forming a gate insulating layer on a surface of the gate electrode comprises:

depositing a high-K dielectric layer on the entire substrate, including the source electrode, drain electrode, and gate electrode; and

selectively removing the high-K dielectric layer using a first hard mask.

13. The method of claim 12 , wherein the high-K dielectric layer remains only on the gate electrode and a peripheral region around the gate electrode.

14. The method of claim 10 , further comprising:

selectively removing the metal silicide layer using a second hard mask.

15. The method of claim 10 , wherein the second conductive layer covers a region above the gate electrode, the source electrode, and the drain electrode.

Assignments (8)