Granted Patent B2

US 7,361,580 · App. 11/473,693 · Granted Apr 22, 2008

Abstract

Claims (32)

1. A semiconductor device, comprising:

a substrate;

a gate insulating layer formed on the substrate;

a gate electrode comprising an upper layer and a lower layer stacked on the gate insulating layer, wherein the lower layer of the gate electrode is formed of amorphous silicon;

an oxide layer on the gate electrode having a portion formed from the gate electrode; and

a sidewall formed on the gate electrode.

2. The semiconductor device of claim 1 , wherein the lower layer is formed of a material having a higher oxidation rate than the upper layer.

3. The semiconductor device of claim 1 , wherein the upper layer and the lower layer have different oxidation rates, respectively.

4. The semiconductor device of claim 1 , wherein the amorphous silicon is formed with a flowrate of silane gas between 50 sccm and 2000 sccm, at a temperature between 500° C. and 550° C., and under a pressure between 10 Pa and 100 Pa.

5. The semiconductor device of claim 1 , wherein the upper layer of the gate electrode comprises polycrystalline silicon.

6. The semiconductor device of claim 5 , wherein the polycrystalline silicon is formed with a flowrate of silane gas between 50 sccm and 2000 sccm, at a temperature between 590° C. and 650° C., and under a pressure between 10 Pa and 100 Pa.

7. The semiconductor device of claim 1 , wherein the upper layer is thicker than the lower layer.

8. The semiconductor device of claim 1 , wherein the lower layer of the gate electrode has a narrower width than that of the upper layer of the gate electrode.

9. The semiconductor device of claim 1 , further comprising an impurity ion region on the semiconductor substrate at both sides of the gate electrode.

10. The semiconductor device of claim 9 , wherein the lower layer of the gate electrode is located between the impurity ion regions such that the lower layer does not overlap with the impurity ion regions.

11. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating layer on a substrate;

forming a lower layer and an upper layer on the gate insulating layer;

etching the upper layer and the lower layer to form a gate electrode;

etching the gate insulating layer by using only the gate electrode as a mask;

forming an oxide layer by performing a heat treatment on the substrate and the gate electrode; and

forming a high density impurity region by implanting impurity ions into the semiconductor substrate.

12. The method of claim 11 , wherein the upper and the lower layers have different oxidation rates, respectively.

13. The method of claim 11 , wherein the upper layer is polycrystalline silicon, and the lower layer is amorphous silicon.

14. The method of claim 13 , wherein the upper layer is formed with a flowrate of silane gas between 50 sccm and 2000 sccm, at a temperature between 590° C. and 650° C., and under a pressure between 10 Pa and 100 Pa.

15. The method of claim 13 , wherein the lower layer is formed with a flowrate of silane gas between 50 sccm and 2000 sccm, at a temperature between 500° C. and 550° C., and under a pressure between 10 Pa and 100 Pa.

16. The method of claim 11 , wherein the lower layer has a narrower width than that of the upper layer.

17. The method of claim 11 , further comprising forming a low density impurity region by implanting impurity ions into the semiconductor substrate.

18. The method of claim 17 , wherein the low density impurity region is formed at both sides of the gate electrode.

19. The method of claim 11 , further comprising:

forming a nitride layer on the oxide layer; and

forming sidewalls by etching the oxide layer and the nitride layer.

Assignments (8)