FPGA with hybrid interconnect
View Patent ↗An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing implementations with a hybrid FPGA/ASIC interconnect structure. These implementations retain multi-program capability while requiring a much smaller silicon area than a conventional FPGA when customized for a particular set of user applications.
1. A method, comprising:
comparing, by routing software executing on a computing device, netlists for a plurality of custom logic functionalities to be implemented in an integrated circuit;
from the netlists, identifying, by the routing software, netlist connections common to all of the plurality of custom logic functionalities and netlist connections common to some, but not all, of the plurality of custom logic functionalities; and
creating, by the routing software, a layout for the integrated circuit, wherein the layout includes a plurality of logic cells, a plurality of field-programmable switches, and a plurality of hardwired metal connections, wherein the netlist connections common to all of the plurality of custom logic functionalities are implemented with a first subset of the plurality of hardwired metal connections, and wherein the netlist connections common to some, but not all, of the plurality of custom logic functionalities are implemented by a combination of a second subset of the plurality of hardwired metal connections and the plurality of field-programmable switches.
2. The method of claim 1 , wherein said creating a layout further comprises creating the layout with a plurality of additional field-programmable switches and a plurality of additional logic cells to provide additional programming functionalities.
3. The method of claim 2 , wherein at least one of the additional programming functionalities is an additional custom logic functionality different from each of the plurality of custom logic functionalities.
4. The method of claim 1 , wherein said creating a layout further comprises:
creating a first routing pattern for a first custom logic functionality of the plurality of custom logic functionalities;
creating a second routing pattern for a second custom logic functionality of the plurality of custom logic functionalities by performing rip-up and retry alternations on the first routing pattern;
comparing the first routing pattern and the second routing pattern to determine a first number of programmable connections common to both of the first and second routing patterns;
creating a third routing pattern for the second custom logic functionality;
creating a fourth routing pattern for the first custom logic functionality by performing rip-up and retry alternations on the third routing pattern;
comparing the third routing pattern and the fourth routing pattern to determine a second number of programmable connections common to both of the third and fourth routing patterns;
comparing the first number of programmable connections and the second number of programmable connections; and
choosing the first and second routing patterns for implementation in the layout if the first number of programmable connections is determined to be greater than the second number of programmable connections, or choosing the third and fourth routing patterns for implementation in the layout if the second number of programmable connections is determined to be greater than the first number of programmable connections.
5. A method, comprising:
comparing, by routing software executing on a computing device, a plurality of netlists for a plurality of custom logic functionalities to be implemented in an integrated circuit;
from the netlists, identifying, by the routing software, a first plurality of netlist connections common to all of the plurality of custom logic functionalities and a second plurality of netlist connections common to some, but not all, of the plurality of custom logic functionalities; and
creating, by the routing software, a layout for the integrated circuit, wherein the first plurality of netlist connections are implemented with a first plurality of hardwired metal connections and the second plurality of netlist connections are implemented by a combination of a second plurality of hardwired metal connections and a plurality of field-programmable switches;
wherein the layout includes at least one additional field-programmable switch and at least one additional logic cell that are unnecessary to implement the plurality of custom logic functionalities.