Method of operating a complementary bit resistance memory sensor and method of operation
View Patent ↗A method and apparatus are disclosed for sensing the resistance state of a resistance-based memory element using complementary resistance-based elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.
1. A method of producing a programmable resistance memory device, said method comprising:
forming first and second digit lines;
forming first and second programmable resistance memory elements;
forming first and second access transistors for respectively coupling said first and second memory elements to said first and second digit lines;
forming a precharge circuit for precharging said first and second digit lines to a first voltage;
forming respective row lines for operating said access transistors to couple said memory elements to respective digit lines; and
forming a sense amplifier which has inputs respectively coupled to said digit lines.
2. The method as in claim 1 further comprising forming a row decoder for decoding row address signals and selectively and simultaneously enabling said word lines.
3. The method as in claim 1 wherein said memory elements are fabricated in a common memory array.
4. The method as in claim 1 wherein said memory elements are fabricated in different memory arrays.
5. The method as in claim 1 further comprising forming an equilibrate circuit for equilibrating said digit lines.
6. A method of forming a memory device, the method comprising:
forming an array of memory cells, wherein said act of forming further comprises:
forming first and second digit lines;
forming first and second programmable resistance memory elements;
forming first and second access transistors for respectively coupling said first and second memory elements to said first and second digit lines;
forming a precharge circuit for precharging said first and second digit lines to a first voltage;
forming respective row lines for operating said access transistors to couple said memory elements to respective digit lines; and
forming a sense amplifier which has inputs respectively coupled to said digit lines.
7. The method of claim 6 , wherein said first act of forming further comprises forming a row decoder for decoding row address signals and selectively and simultaneously enabling said word lines.
8. The method of claim 6 , wherein said first act of forming further comprises forming an equilibrate circuit for equilibrating said digit lines.